DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 6-8 and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Takahashi et al. (JP H05198816).
Regarding claim 1, Takahashi teaches an apparatus, comprising:
a pad (Fig. 9B, pad 23) above a semiconductor substrate (substrate 11);
an n-well (n-well 12) in the semiconductor substrate; and
a floating p-well (floating p-well 20, see translation page 2) in the semiconductor substrate, the floating p-well below the pad and surrounded by the n-well in the semiconductor substrate (see Fig. 9B).
Regarding claim 2, Takahashi teaches the apparatus according to claim 1, further comprising a deep n-well (deep n-well 11) in the semiconductor substrate, wherein the floating p-well is surrounded by the n-well and the deep n-well (Fig. 9B).
Regarding claim 3, Takahashi teaches the apparatus according to claim 2, wherein the deep n-well is under the n-well (see Fig. 9B).
Regarding claim 6, Takahashi teaches the apparatus according to claim 1, wherein the pad is coupled to a gate of a transistor (pad 23 is a gate pad).
Regarding claim 7, Takahashi teaches the apparatus according to claim 1, wherein the pad is coupled to a gate of a MOSFET (transistor in Fig. 9B is a MOSFET).
Regarding claim 8, Takahashi teaches the apparatus according to claim 1, wherein the n-well is greater in size than the pad in a plan view (see Fig. 9B).
Regarding claim 10, Takahashi teaches the apparatus according to claim 1, wherein the pad is a first pad, and
the apparatus further comprises a second pad above the semiconductor substrate, the second pad arranged apart from the first pad in a horizontal direction (see Fig. 8A, gate pad is labeled 4, source pad is labeled 3).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 11-12 and 14-16 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi in view of Asano et al. (JP 2006/202814).
Regarding claim 4, Takahashi teaches the apparatus according to claim 1, but does not teach wherein the pad is configured to be electrically probed during testing.
However, Asano teaches another semiconductor which includes a gate pad that is probed during testing (see Asani Fig. 12B, gate pad 506 is probed during testing). It would have been obvious to a person of skill in the art at the time of the effective filing date that the FET of Takahashi could have been part of a TEG and therefore probed because Asano teaches that this allows for testing/prediction of the characteristics of the rest of the transistors in the device (see Asano “background art” section).
Regarding claim 11, Takahashi teaches an apparatus, comprising:
a pad (Fig. 9B, pad 23) above a semiconductor substrate (substrate 11);
an n-well (n-well 12) in the semiconductor substrate;
a deep n-well (deep n-well 11) in the semiconductor substrate, the deep n-well under the n-well (Fig. 9B); and
a floating p-well (Fig. 9B, floating P well 20) in the semiconductor substrate, the floating p-well below the pad (Fig. 9B) and surrounded by the n-well and the deep n-well in the semiconductor substrate (Fig. 9B).
Takahashi does not teach the pad configured to be electrically probed during testing. However, Asano teaches another semiconductor which includes a gate pad that is probed during testing (see Asani Fig. 12B, gate pad 506 is probed during testing). It would have been obvious to a person of skill in the art at the time of the effective filing date that the FET of Takahashi could have been part of a TEG and therefore probed because Asano teaches that this allows for testing/prediction of the characteristics of the rest of the transistors in the device (see Asano “background art” section).
Regarding claim 12, Takahashi in view of Asano teaches the apparatus according to claim 11, wherein the pad is configured to be coupled to a testing probe (see Asano Fig. 12, test probe 10) of a test apparatus (inherent that the test probe must be connected to a test apparatus or it will be incapable of testing).
Regarding claim 14, Takahashi in view of Asano teaches the apparatus according to claim 11, wherein the pad is coupled to a gate of a transistor (pad 23 is a gate pad).
Regarding claim 15, Takahashi in view of Asano teaches the apparatus according to claim 11, wherein the n-well is greater in size than the pad in a plan view to surround entirety of the pad (see Fig. 9B and 8A, n-well is entire wafer area, while pad is only a small portion).
Regarding claim 16, Takahashi in view of Asano teaches the apparatus according to claim 11, wherein the pad is a first pad, and the apparatus further comprises a second pad (second pad 3, Fig. 8A) above the semiconductor substrate, the second pad in the same layer as the first pad (Fig. 8A and paragraph [0009]-[0011])) and arranged apart from the first pad in a horizontal direction (Fig. 8A).
Allowable Subject Matter
Claims 5, 9 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claims 5 and 13, the prior art, alone or in combination, fails to teach or suggest the pad coupled to a capacitance element.
Regarding claim 9, the prior art, alone or in combination, fails to teach or suggest at least one of an n+ plug and a p+ plug above the semiconductor substrate, wherein the p-well is surrounded by the at least one of the n+ plug and the p+ plug.
Claims 17-20 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claims 17-20, the prior art, alone or in combination, fails to teach or suggest the pad coupled to a capacitance element.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Evan G Clinton whose telephone number is (571)270-0525. The examiner can normally be reached Monday-Friday at 8:30am to 5:30pm.
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/EVAN G CLINTON/Primary Examiner, Art Unit 2899