DETAILED ACTION
Claims 1, 4-5, 7-10, 12 and 13 are pending in the Instant Application.
Claims 1, 4-5, 7-10, 12 and 13 are rejected (Final Rejection).
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 4-5, 7-10, 12 and 13 are rejected under 35 U.S.C. 102(a)(1) as being unpatentable by Oberai et al. (“Oberai”), United States Patent Application Publication No. 2021/0406441.
As per claim 1, Oberai discloses an information processing method executed by a computer, the method comprising:
generating processed data obtained by processing original data including a group of a plurality of data values arranged respectively at position coordinates along a predetermined direction on a map ([0026] wherein original data is the reported defect data respectively at position coordinates and size and are processed into coordinates in the CAD system),
using a processing pattern in which a processing rule of the original data is defined for each position coordinate on the map ([0030] wherein a processing pattern, overlapping polygons with defect data, is used for each position in the map);
acquiring a plurality of pieces of original data ([0026] wherein the original data is acquired for the wafer, including areas including and not including defects); and
by using a same replacement function for each of the plurality of pieces of original data, replacing position coordinates of at least part of a plurality of data values in an analysis target region in each of the plurality of pieces of the original data with other position coordinates in the analysis target region ([0030] wherein each defect in the replacement function is replaced as noted in [0046] by CAD identifiers), wherein the processing pattern is:
a pattern defining the processing rule for processing a data value in the original data into a processed data value in the processed data for each position coordinate ([0026] wherein a pattern can be the physical layout structures of the wafer), and a pattern defining any of a retainment code representing that the data value in the original data is to be used as it is, a deletion code representing that the data value is to be deleted, and a non-analysis target code representing that the data value is not to be analyzed, for each position coordinate ([0030] wherein for each position coordinate, retainment code exists representing data where no defect is determined, a deletion code representing an area where the defect is associated with an area of the chip without a structure (where null is associated with the delete) and a non-analysis target code is used for a given defect on the chip), and the generating includes: generating the processed data using one of a plurality of processing patterns with processing rules that are at least partially different from one another ([0030] wherein certain false positive defects may be remove, making it different), the one having a data size matching a data size of the original data ([0026] wherein the coordinates on the wafer and the CAD system (processed system) are usually the same, including in size since one is overlayed on another), and generating the processed data obtained by processing each of a plurality of pieces of shuffled data in which the position coordinates are replaced at the replacing, using the processing pattern ([0059]
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and [Fig. 7] wherein the filtered defects are generated as shown).
.*Shown is the original data and the processed data according to Fig. 7
As per claim 4, Oberai discloses the method according to claim 1, wherein the processing pattern is a pattern in which the retainment code is defined at the position coordinates in a region having a shape similar to a shape of an analysis target region in the original data ([0026] wherein coordinates in the original wafer data for non-defect areas (retainment code) are the same in the CAD system), and the non-analysis target code or the deletion code is defined in an outer periphery of the region in which the retainment code is defined ([0030] wherein defect data, which includes non-analysis target code and deletion code are separate and distinct from the non-defect retainment code areas).
As per claim 5, Oberai discloses the method according to claim 1, wherein the generating includes generating the processed data using, according to the original data, one of a plurality of processing patterns with processing rules that are at least partially different from one another ([0030] wherein at least one difference is that if a defect occurs in a part of the wafer that has no components, than the defect is deleted and replaced with a null).
As per claim 7, Oberai disclosed the method according to claim 1, further comprising outputting a plurality of processing patterns having different processing rules, to an output unit, wherein the generating includes generating the processed data using one selected from the plurality of output processing patterns ([0026] wherein different physical layouts structures (processing patterns) are output by overlying them on the different images, which have different processing rules based on locations on the wafer as described).
As per claim 8, Oberai discloses t yeah he method according to claim 1, further comprising outputting the processing pattern used for processing the original data in the generating, to an output unit ([0026] wherein the critical structures based on the processing pattern is output for further review) .
As per claim 9, Oberai discloses the method according to claim 1, wherein the predetermined direction includes K-dimensional directions including a first direction on the map and a second direction intersecting the first direction, K being an integer of 2 or more ([0026] wherein the coordinates (implying at least two directions intersecting) have corresponding coordinates.)
As per claim 10, Oberai discloses the method according to claim 1, wherein the predetermined direction is a one-dimensional direction on the map ([0037] wherein a single dimension of cells is described to generate processed data).
As per claim 12, Oberai discloses an information processing apparatus, comprising: one or more hardware processors ([0080]) configured to perform the method of claim 1. Therefore, the claim is rejected for the same rationale and reasoning as claim 1.
As per claim 13, Claim 13 is the computer program product that performs the method of claim 1 and is rejected for the same rationale and reasoning.
Response to Arguments
Applicant’s arguments with respect to claims 1, 4-5, 7-10, 12 and 13 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KANNAN SHANMUGASUNDARAM whose telephone number is (571)270-7763. The examiner can normally be reached M-F 9:00 AM -6:00 PM.
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/KANNAN SHANMUGASUNDARAM/Primary Examiner, Art Unit 2168