DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to applicant’s Restriction/Election filed on 06/22/2026.
Currently claims 1-20 are pending in the application.
Election/Restrictions
Applicant's election without traverse of Species A, claims 1-10 and 16-20, in the reply filed on 06/22/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/28/2023 and 07/29/2024 were filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements were considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-10 are rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Regarding claim 1, the instant claim recites "a lower gate electrode and a lower active contact which are spaced apart from each other in a first direction perpendicular to the first surface" and "an upper gate electrode and an upper active contact, which are spaced apart from each other in the first direction." The first direction is defined as perpendicular to the first surface (i.e., the vertical/stacking direction). However, the specification and the remaining claims indicate that a gate electrode and its neighboring active contact within the same active region are laterally adjacent structures: claim 7 recites the cutting structure "between the lower gate electrode and the lower active contact, and between the upper gate electrode and the upper active contact," as a line-shaped pattern extending in a direction parallel to the substrate surface in plan view, which is only consistent with lateral (in-plane) separation. It is therefore unclear whether Applicant intends the gate electrode and active contact to be spaced vertically (as literally claimed, which appears inconsistent with the disclosed cell layout) or horizontally. The metes and bounds of the claim cannot be ascertained.
Claims 2–10 are rejected for depending from claim 1. For purposes of examination, the limitation is interpreted as set forth in the Claim Interpretation section above. Suggested amendment: "spaced apart from each other in a second direction parallel to the first surface" (with conforming amendment for the upper gate electrode/upper active contact).
Claims 7 and 8 are further rejected under 35 U.S.C. 112(b) as being indefinite. Claim 7 recites "a direction parallel to an upper surface of the substrate." Claim 1, from which claim 7 depends, defines the substrate as having a "first surface" and a "second surface" that are opposite to each other; it is unclear whether "an upper surface" refers to the first surface, the second surface, or some other surface, particularly because the claimed device has structure on both surfaces and the orientation of the device is not fixed. There is insufficient antecedent basis for "an upper surface of the substrate" as a distinct surface. Suggested amendment: "a direction parallel to the first surface of the substrate." Claim 8 is rejected for depending from claim 7.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 4-6 are rejected under 35 U.S.C. 102 (a) (2) as being anticipated by US 2023/0345690 A1 (Xie).
Regarding claim 1, Xie discloses, a semiconductor memory device, comprising: a substrate (as annotated on Fig. 4; [0032]) including a first surface (top) and a second surface (bottom), the first and second surfaces of the substrate being opposite to each other (as evident on Fig. 4);
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a lower active region (as annotated on Fig. 3; [0028] – [0029], [0057]) on the first surface (top), the lower active region comprising a lower gate electrode (gates of PD1, PD2, PG2) and a lower active contact (backside self-aligned S/D contacts BSCA 621–625 contacting the S/D regions of the lower-tier devices; Fig. 17; [0050]) which are spaced apart from each other in a first direction (the examiner interpreted it as laterally) perpendicular to the first surface (the gate electrodes and S/D contacts are laterally spaced along the cell; Fig. 17; [0050]);
an upper active region (as annotated on Fig. 3; [0028] – [0029], [0057]) stacked on the lower active region in the first direction (as annotated on Fig. 3; [0028] – [0029], [0057]), the upper active region comprising an upper gate electrode (gates of PU1, PU2, PG1) and an upper active contact (CA 611–614/CB 615–616; Fig. 14; [0044]–[0045]), which are spaced apart from each other in the first direction (the examiner interpreted it as laterally);
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a first metal layer on the first surface (Xie teaches frontside local interconnects LI 631–633, bit line 711, word line 712, VDD line 713, and BEOL layers 801, formed of metal W, Co, Ru, and/or Cu) on the frontside (Figs 14 and 15; [0046]–[0048], [0054]); and
Note: Xie teaches in para. [0049] that after the handling wafer 802 is wafer-bonded onto the BEOL layers 801 at a frontside, the SRAM device 100 may be flipped upside down such that processing may continue at a backside of the SRAM device 100. Here, for the sake of illustration, the drawings are not shown upside down. However, as may be noticed from various illustrations hereafter, processing continues at the backside (bottoms of the drawings) of the SRAM device 100. More particularly, the substrate 110 may be first removed through a wafer grinding, CMP, and/or other etch processes.
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a back-side metal layer on the second surface (Xie teaches backside local interconnects LI 641–643, second bit line 721, VSS line 722, second word line 723, and backside BEOL layers 803, formed of metal on the backside; Fig. 19; [0052]–[0054]),
wherein the back-side metal layer comprises a first shared pad electrically connecting the lower gate electrode to the lower active contact (Fig. 19; [0050] – [0052]; Xie teaches in para. [0050] – [0052] that the backside local interconnect LI 641 connecting BSCA contact 621 and BSCA contact 622 (lower active contacts on S/D regions of the lower-tier PG2/PD2) to BSCB contact 626, which contacts the gate of the lower-tier transistor PD1) and
the first metal layer comprises a second shared pad electrically connecting the upper gate electrode to the upper active contact (Fig. 14; [0045]–[0046]; Xie teaches in para. [0045] – [0046] that the frontside local interconnect LI 631 connecting CA contact 611 (upper active contact on the S/D region of upper-tier PG1) and the first internal contact 610 to CB contact 616, which contacts the common gate of the second inverter including the upper-tier PU2 gate electrode).
Regarding claim 4, Xie discloses, the backside node (LI 641, connecting the drain side of one inverter to the gate of the other) and the frontside node (LI 631) form the cross-coupled storage nodes of the 6T SRAM cell — i.e., the first shared pad is configured as an output terminal of a first inverter and the second shared pad is configured as an output terminal of the second inverter of the SRAM cell ([0029] (cross-couple connections of S/D regions to opposite-inverter gates); Figs. 3, 14 and 19; [0046], [0052]).
Regarding claim 5, Xie discloses, the back-side metal layer further comprising a power line (VSS power supply line 722 formed on the backside; Fig. 19; [0053]).
Regarding claim 6, Xie discloses, the first metal layer further comprising a bit line (first bit line 711 formed on the frontside; Fig. 14; [0047]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0345690 A1 (Xie).
Regarding claim 2, Xie discloses, the first and second shared pads (LI 641; LI 631) within the compact footprint of a single 6T cell in which the complementary inverters are vertically stacked and share common gates ([0028], [0046], [0052]).
But Xie fails to teach explicitly that the two pads vertically overlap in plan view.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date to lay out the backside node pad and the frontside node pad so that they vertically overlap, because the two cross-couple straps span the same small cell area between the two gate columns and the two S/D columns, and arranging wiring on opposite sides of the same footprint to overlap is a mere rearrangement of parts that does not modify the operation of the device (MPEP 2144.04(VI)(C)); the skilled artisan would have been motivated to overlap the pads to minimize cell area and maximize integration density, the very benefit of moving one node to the backside. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0076] – [0077] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Regarding claim 3, Xie fails to teach explicitly, the semiconductor memory device of claim 2, wherein an area of the first shared pad, in a plan view, is different from an area of the second shared pad.
However, each pad needs only to be large enough to land on its respective gate contact and active contact (Xie [0046], [0052]), and the backside pad additionally accommodates deep-via landing ([0053]). A mere change in the size or proportion of a component is within the level of ordinary skill absent unexpected results (MPEP 2144.04(IV)(A)); sizing each pad to its own routing constraints naturally yields different areas. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0076] – [0077] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Claims 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0345690 A1 (Xie) as applied to claim 1 and further in view of US 2022/0102362 A1 (Chanemougame).
Regarding claim 7, Xie fails to teach explicitly, the semiconductor memory device of claim 1, further comprising a cutting structure between the lower gate electrode and the lower active contact, and between the upper gate electrode and the upper active contact, wherein the cutting structure is a line-shaped pattern, which extends in a direction parallel to an upper surface of the substrate, when viewed in a plan view.
However, in analogous art, Chanemougame discloses dielectric cutting structures for such cells - a CT patterning layer that runs perpendicular to the gates and is at the cell boundaries and in the middle of the cell, whose purpose "is to insert a dielectric separation in these locations only," forming line-shaped separation pillars SP between inverters and between adjacent cells ([0059], [0061]–[0063]), together with a CT_T layer providing separation between stacked device levels ([0066]–[0068]); the CT/CT_T shapes are line-shaped patterns extending parallel to the substrate surface in plan view and are located between gate structures and adjacent contact/active structures of the cell.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie and Chanemougame before him/her, to modify the teachings of a stacked SRAM cell as taught by Xie and to include the teachings of line-shaped dielectric cutting structure as taught by Chanemougame since dielectric cutting structures separate the gates and node structures of adjacent cell portions in a dense, repeated array using a self-aligned etch that tolerates edge-placement error and enables tighter integration ([0062]–[0063], [0065]). The combination is the use of a known technique (dielectric cut/separation pillar) to improve a similar device in the same way, with predictable results (MPEP 2143(I)(C)–(D)). Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Chanemougame while forming a stacked SRAM cell of Xie.
Regarding claim 8, the combination of Xie and Chanemougame discloses, the semiconductor memory device of claim 7, wherein the cutting structure extends into the lower active region and the upper active region (Chanemougame teaches that separation pillars between inverters extend through the stack; the CT_T cut extends into the active levels to separate bottom devices from the devices on top; (Figs. 8 and 9; [0059], [0066]–[0068], [0071]–[0072]), meeting "the cutting structure extends into the lower active region and the upper active region".
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Regarding claim 9, Xie discloses stacked lower and upper devices using fin-type channel patterns (Fig. 4; [0032] - [0033]).
But Xie fails to teach explicitly, the semiconductor memory device of claim 1, wherein the lower active region comprises a first semiconductor pattern and a second semiconductor pattern on the first semiconductor pattern, the lower gate electrode extends around the first and second semiconductor patterns, the upper active region comprises a third semiconductor pattern and a fourth semiconductor pattern on the third semiconductor pattern, and the upper gate electrode extends around the third and fourth semiconductor patterns.
However, in analogous art, Chanemougame discloses, two-deck stacked SRAM transistors as lateral gate-all-around nanosheet (LGAA NS) devices ([0037]-[0038]), each device having a plurality of vertically stacked nanosheet channels with the gate surrounding the channels, and teaches adjusting the number of nanosheets per device (Fig. 15B; [0084]). Chanemougame teaches in para. [0084] that one nano-sheet NS for the top PMOS pull-up transistors PU1 and PU2, and two nano-sheets NS for the bottom NMOS pull-down transistors PD1 and PD2, and pass-gates PG1 and PG2.
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie and Chanemougame before him/her, to modify the teachings of a stacked SRAM cell as taught by Xie and to include the teachings of various semiconductor regions separated by line-shaped dielectric cutting structure as taught by Chanemougame since in MPEP 2143(I)(B), it is stated that a simple substitution of one known element for another to obtain predictable results is obvious. In the instant application, it is a simple substitution of one known channel architecture for another yielding the predictable benefits of improved electrostatic control and drive-current tunability in the same stacked-SRAM context. Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Chanemougame while forming a stacked SRAM cell of Xie.
Regarding claim 10, Xie discloses, first and second pull-up transistors stacked with first and second pull-down transistors in vertical alignment, with the PU transistors on top of the PD transistors (Fig. 3; [0027] - [0028]), i.e., the inverse of the claimed orientation (lower active region comprising the pull-up transistors; pull-down stacked on pull-up).
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However, Chanemougame teaches that in CFET stacking the NMOS device may be stacked on top of the PMOS device "(or vice versa)" (Fig. 1; [0038]), establishing that the vertical ordering of the complementary devices is a known, interchangeable design option. With this teaching, it is well within the purview of a person with ordinary skill in the art to make “the lower active region comprising a first pull-up transistor and a second pull-up transistor, the upper active region comprises a first pull-down transistor and a second pull-down transistor, the first pull-down transistor is stacked on the first pull-up transistor in the first direction, and the second pull-down transistor is stacked on the second pull-up transistor in the first direction”.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie and Chanemougame before him/her, to modify the teachings of a stacked SRAM cell as taught by Xie and to include the teachings of CFET stacking of the NMOS device on top of the PMOS device as taught by Chanemougame since in MPEP 2143 (I) ( E), it is stated that it is "Obvious to try" – choosing from a finite number of identified, predictable solutions, with a reasonable expectation of success and another teaching of a mere reversal of parts that does not change the principle of operation of the cross-coupled cell (MPEP 2144.04(VI)(A)). Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Chanemougame while forming a stacked SRAM cell of Xie.
Claims 16-20 are rejected under 35 U.S.C. 103 as being unpatentable over US 2023/0345690 A1 (Xie) and further in view of US 2022/0102362 A1 (Chanemougame).
Regarding claim 16, Xie discloses, a semiconductor memory device, comprising: a substrate (as annotated on Fig. 4; [0032]) including a first surface (top) and a second surface (bottom), the first and second surfaces of the substrate being opposite to each other (as evident on Fig. 4);
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a lower active region (as annotated on Fig. 3; [0028] – [0029], [0057]) on the first surface (top), the lower active region comprising a lower channel pattern and a lower source/drain pattern lower-tier PD/PG devices with fin channel patterns and epitaxial S/D regions);
an upper active region (as annotated on Fig. 3; [0028] – [0029], [0057]) stacked on the lower active region in a first direction (vertical) perpendicular to the first surface (top), the upper active region comprising an upper channel pattern and an upper source/drain pattern upper-tier PU/PG devices stacked thereon ([0028], [0033], [0035], [0057]);
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a lower gate electrode (gates of the lower-tier) on the lower channel pattern (including common gates connecting stacked PU/PD pairs ([0028], [0057]; Fig. 22, step 930);
an upper gate electrode (gates of the upper-tier) on the upper channel pattern (including common gates connecting stacked PU/PD pairs ([0028], [0057]; Fig. 22, step 930);
an interlayer insulating layer (frontside dielectric through which the CA/CB contacts are formed over the upper tier; Fig. 14 and 19; [0044]–[0045]) on the upper gate electrode and the upper source/drain pattern;
a lower active contact (BSCA 621–625) extending into the substrate and electrically connected to the lower source/drain pattern (backside self-aligned S/D contacts BSCA 621–625 formed by replacing the dielectric material 304 within the base/substrate region, contacting the lower-tier S/D regions; Fig. 17; [0050]);
an upper active contact (frontside CA contacts 611–614) extending into the interlayer insulating layer and electrically connected to the upper source/drain pattern (Fig. 14; [0045]);
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a back-side metal layer (backside LIs 641–643/BEOL 803; Fig. 19; [0052]) on the second surface of the substrate;
a lower via electrically connecting the back-side metal layer to the lower active contact (deep vias (type-A) and short vias (type-B) connecting backside lines to the BSCA contacts/LIs, e.g., second bit line 721 to BSCA 623 and VSS 722 to BSCA 624; Fig. 19; [0053]);
a first metal layer (frontside LIs 631–633/bit line 711/word line 712/VDD 713; (Figs. 14 and 15; [0046] – [0048]) on the interlayer insulating layer;
an upper via (deep (type-A) and short (type-B) vias to the CA contacts; Figs. 14 and 15; [0046]–[0048]) electrically connecting the first metal layer to the upper active contact; and
But Xie fails to teach explicitly, a cutting structure extending into the lower gate electrode, the lower active contact, the upper gate electrode, and the upper active contact.
However, in analogous art, Chanemougame discloses, line-shaped dielectric separation (CT layer/separation pillars SP; CT_T layer; Figs. 5-8) at cell boundaries and mid-cell, running perpendicular to the gates and extending vertically through both device decks to divide gate and node structures of adjacent cell portions (Figs. 5-8; [0059], [0061]–[0063], [0066]–[0068]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Xie and Chanemougame before him/her, to modify the teachings of a stacked SRAM cell as taught by Xie and to include the teachings of line-shaped dielectric cutting structure as taught by Chanemougame since dielectric cutting structures separate the gates and node structures of adjacent cell portions in a dense, repeated array using a self-aligned etch that tolerates edge-placement error and enables tighter integration ([0062]–[0063], [0065]). The combination is the use of a known technique (dielectric cut/separation pillar) to improve a similar device in the same way, with predictable results (MPEP 2143(I)(C)–(D)). Absent this important teaching in Xie, a person with ordinary skill in the art would be motivated to reach out to Chanemougame while forming a stacked SRAM cell of Xie.
Regarding claim 17, the combination of Xie and Chanemougame discloses, the dielectric cut divides otherwise continuous structures into separate segments — the pillar formed by CT "separates the gate of the first inverter INV1 from inverters of adjacent cells" and from the other inverter of the same cell ([0063]); in the combination, the line-shaped cutting structure crossing the cell likewise divides the lower gate electrode, lower active contact, upper gate electrode, and upper active contact each into first and second segments on opposite sides of the cut, as claimed (Chanemougame Ref.).
With this teaching, it is well within the purview of a person with ordinary skill in the art to make, “the semiconductor memory device of claim 16, wherein the lower gate electrode is divided into a first lower gate electrode and a second lower gate electrode by the cutting structure, the lower active contact is divided into a first lower active contact and a second lower active contact by the cutting structure, the upper gate electrode is divided into a first upper gate electrode and a second upper gate electrode by the cutting structure, and the upper active contact is divided into a first upper active contact and a second upper active contact by the cutting structure.”
Regarding claim 18, Xie discloses, Xie discloses the back-side metal layer comprising a first shared pad electrically connecting a first lower gate electrode to a second lower active contact (backside LI 641 connecting gate contact BSCB 626 of the first pull-down transistor to BSCA contacts 621/622 on S/D regions of the other, cross-coupled devices) and the first metal layer comprising a second shared pad electrically connecting a second upper gate electrode to a first upper active contact (frontside LI 631 connecting CB 616 on the second-inverter gate to CA 611/internal contact 610) ([0029], [0045]–[0046], [0051]–[0052]) — the claimed diagonal (cross-couple) connectivity.
With this teaching, it is well within the purview of a person with ordinary skill in the art to make, “the semiconductor memory device of claim 17, wherein the back-side metal layer comprises a first shared pad electrically connecting the first lower gate electrode to the second lower active contact, and the first metal layer comprises a second shared pad electrically connecting the second upper gate electrode to the first upper active contact”.
Regarding claim 19, Xie discloses, the first and second shared pads (LI 641; LI 631) within the compact footprint of a single 6T cell in which the complementary inverters are vertically stacked and share common gates ([0028], [0046], [0052]).
But the combination of Xie and Chanemougame fails to teach explicitly, the semiconductor memory device of claim 18, the two pads vertically overlap in plan view.
However, it would have been obvious to a person having ordinary skill in the art before the effective filing date to lay out the backside node pad and the frontside node pad so that they vertically overlap, because the two cross-couple straps span the same small cell area between the two gate columns and the two S/D columns, and arranging wiring on opposite sides of the same footprint to overlap is a mere rearrangement of parts that does not modify the operation of the device (MPEP 2144.04(VI)(C)); the skilled artisan would have been motivated to overlap the pads to minimize cell area and maximize integration density, the very benefit of moving one node to the backside. Furthermore, the applicant has not presented persuasive evidence in Spec. para. [0076] – [0077] that the claimed arrangements are for a particular purpose that is critical to the overall claimed invention (i.e. the invention would not work without the specific claimed arrangements). Also, the applicant has not shown that the claimed arrangements produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art.
Regarding claim 20, Xie discloses, the semiconductor memory device of claim 16, wherein the back-side metal layer comprising a power line (VSS 722, [0053]) and the first metal layer comprising a bit line (711, [0047]).
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0115388 A1 (Hirose) - A semiconductor memory device is disclosed including a 2-port SRAM cell, the 2-port SRAM cell including: a first transistor having one node connected to a first power source that supplies a first voltage, another node connected to a first node, and a gate connected to a second node; a second transistor having one node connected to the first power source, another node connected to the second node, and a gate connected to the first node; a third transistor having one node connected to the first node, another node connected to a second power source that supplies a second voltage different from the first voltage, and a gate connected to the second node; a fourth transistor having one node connected to the second node, another node connected to the second power source, and a gate connected to the first node; a fifth transistor having one node connected to a first write-bit line, another node connected to the first node, and a gate connected to a write-word line; a sixth transistor having one node connected to a second write-bit line constituting a complementary bit line pair with the first write-bit line, another node connected to the second node, and a gate connected to the write-word line; a seventh transistor having one node connected to the second power source, and a gate connected to the second node; and an eighth transistor having one node connected to the other node of the seventh transistor, another node connected to a read-bit line, and a gate connected to a read-word line.
US 2022/0108992 A1 (Yamagami) – A Static Random Access Memory (SRAM) cell using Complementary FET (CFET) is disclosed including the first to sixth transistors each of which is a three-dimensional transistor. The first to fourth transistors are formed at the same position as each other in the first direction in which channel portions of the first to sixth transistors extend. The fifth transistor having a node connected to the first bit line and the sixth transistor having a node connected to the second bit line are formed at the same position in the first direction as each other.
US 2021/0366906 A1 (Huang) - A semiconductor structure is disclosed including a power rail, a first source/drain feature disposed over the power rail, a via connecting the power rail to the first source/drain feature; an isolation feature disposed over the first source/drain feature, and a second source/drain feature disposed over the isolation feature, where the first and the second source/drain features are of opposite conductivity types.
Examiner’s Note on Patentability
The limitations most likely to support patentability upon amendment or argument are (i) the express plan-view vertical overlap of the two complementary shared node pads (claims 2, 19) combined with (ii) the cutting structure extending into all four of the lower gate electrode, lower active contact, upper gate electrode, and upper active contact (claims 16–17). Neither Xie nor Chanemougame expressly illustrates both features in a single embodiment; the rejections of those claims rest on rearrangement/design-choice and known-technique rationales. An amendment to claim 1 incorporating the claim 2 overlap together with the claim 7/16 cutting structure, supported by a showing of the specific area/complexity benefit described in para. [0136] – [0137] of the instant specification, would place the case in better condition for allowance, subject to updated search.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
07/08/2026
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