Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on October 28th, 2025 has been entered.
Response to Amendment
The amendment filed October 22nd, 2025 has been entered. Claims 1-3, 5-11, and 13-16 are pending in this application. Applicant’s amendments to the claims have overcome each and every objection previously set forth in the previous Office Action mailed July 29th, 2025. Applicant’s amendments to the claims have been fully considered. The previous rejections set forth in the prior Office action have been withdrawn in light of the claim amendments and/or applicant’s arguments, which have been found persuasive with respect to the prior art previously relied upon. However, upon further consideration of the amended claims, a new ground(s) of rejection is made in view of Srinivasan, in view of Lin et al. (US 11,175,988), hereinafter Lin, and further in view of Lastras-Montano (US 2008/0163032).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 5-6, 9-11, and 15-16 are rejected under 35 U.S.C. 103 as being unpatentable over Srinivasan et al. (US 11,500,719), hereinafter Srinivasan, in view of Lin et al. (US 11,175,988), hereinafter Lin, and further in view of Lastras-Montano (US 2008/0163032).
Regarding claim 1, Srinivasan teaches a storage controller (Srinivasan, col. 11, lines 20-22, “process 900 can be performed by host processor, an acceleration engine, a memory controller, or other components that can access the memory system”) configured to:
generate a plurality of parity values by matching each of a plurality of first bit combinations corresponding to a number of error bits included in a target data set to positions of the error bits (Srinivasan, Fig. 9, block 906, col. 11, lines 40-42, "At block 906, error correction bits based on the set of data bits stored at the source location can be computed. For example, each error correction bit can be computed from a different combination of a subset of the data bits"; the error correction bits equate to parity values); and
determine a corrected bit combination among the plurality of first bit combinations by comparing each of the plurality of parity values with a pre-generated parity value corresponding to the target data set (Srinivasan, Fig. 9, block 918 & block 920, col. 11, lines 55-63, " At block 918, if it is determined that the set of data bits has a correctable error based on the comparison of the error correction bits with the previously stored error correction code [e.g., the location of the erroneous bit(s) can be identified using ECC], then the set of data bits can corrected based on the ECC comparison... at block 920, the corrected set of data bits can be outputted as output data").
Srinivasan fails to teach the generation of the plurality of parity values when the number of the error bits is less than a first reference value and stop determining the corrected bit combination except when there is only one parity value among the plurality of parity values, that is equal to the pre-generated parity value.
However, Lin, in an analogous art, teaches when the number of the error bits is less than a first reference value (Lin, col. 5, lines 21-25, "when the quantity of the error bits of the read data is not greater than n, in step S360, the ECC engine 250 performs an error correction procedure on the read data”; the error correction procedure can equate to generating parity values).
Srinivasan and Lin are both considered to be analogous to the claimed invention because both are in the same field of improving the reliability of memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Srinivasan to incorporate the teachings of Lin by including the functionality of performing error correction procedures when the number of error bits are less than a threshold value.
The suggestion/motivation for doing so would be to determine if the error bits are correctable (Lin, col. 5, lines 10-12, “Therefore, when the quantity of the error bits is not greater than 3, the error bits may be corrected by the ECC engine 250”).
The combination of Srinivasan in view of Lin, taken singly or combined, fails to teach stop determining the corrected bit combination except when there is only one parity value among the plurality of parity values, that is equal to the pre-generated parity value.
However, Lastras-Montano, in an analogous art teaches stop determining the corrected bit combination (Lastras-Montano, Fig. 13, block 1316, para. [0069], lines 16-18, “At block 1316, the error is determined to be an uncorrectable error. In exemplary embodiments, the system operation will halt,”; para. [0067], lines 9-19, “The exemplary process in FIG. 13 implements an error handling policy that corrects an error only when: (1) exactly one chip [also referred to herein as a memory device] signature is the "all zeros" vector… Any other syndromes are trapped and correction is not attempted since this could result in mis-correction, with erroneous data being utilized” [shortened for brevity]) except when (Lastras-Montano, Fig. 13, blocks 1318 & 1320, para. [0070], lines 1-4, “If, at block 1318, it is determined that the trapping set does not contain the signature of any of the chips [i.e., the error is correctable], then block 1320 is performed to correct the error”) there is only one parity value among the plurality of parity values, that is equal to the pre-generated parity value (Lastras-Montano, Fig. 13, blocks 1314 & 1318, para. [0069], lines 4-8, “Next, block 1314 is performed to determine if the signature of exactly one chip is all zeros [i.e, if the error is a correctable error]. If the signature of exactly one chip is all zeros, then block 1318 is performed to determine if the signature of any chip is in the trapping set”).
Srinivasan, Lin, and Lastras-Montano are all considered to be analogous to the claimed invention because all three are in the same field of improving the reliability of memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Srinivasan in view of Lin to incorporate the teachings of Lastras-Montano by including the functionality of stopping the determination of a corrected bit combination, unless there is a single parity value match to a pre-generated parity value.
The suggestion/motivation for doing so would be to prevent the mis-correction of data and the utilization of erroneous data (Lastras-Montano, para. [0067], lines 16-19, “Any other syndromes are trapped and correction is not attempted since this could result in mis-correction, with erroneous data being utilized”).
Regarding claim 2, the combination of Srinivasan in view of Lin, further in view of Lastras-Montano teaches the storage controller according to claim 1, wherein the storage controller is configured to generate recovered data corresponding to the target data set by matching the corrected bit combination to the positions of the error bits (Srinivasan, col. 12, lines 48-51, "At block 1012, the data bits in the set of data bits determined to be erroneous can be inverted to generate a set of recovered data bits, and the set of recovered data bits can be used as the read data").
Regarding claim 3, the combination of Srinivasan in view of Lin, further in view of Lastras-Montano teaches the storage controller according to claim 1, wherein the storage controller is configured to determine, as the corrected bit combination, a bit combination corresponding to a first parity value of the plurality of parity values among the plurality of first bit combinations when the first parity value is equal to the pre-generated parity value (Srinivasan, col. 6, lines 14-19, "Those of the parity bits that mismatch with the computed parity check bits can indicate which bits of the 16-bit data word originally read from the memory channel is erroneous. The erroneous bits can then be inverted to recover the correct 16-bit work, and the recovered 16-bit word can be outputted").
Regarding claim 5, the combination of Srinivasan in view of Lin, further in view of Lastras-Montano teaches the storage controller according to claim 1, wherein:
the target data set comprises a plurality of data areas and a parity area (Srinivasan, Fig. 2, data 214, parity 256); and
the parity area is configured to store the pre-generated parity value (Srinivasan, col. 5, lines 2-4, “Parity memory channel can be used to store parity bits that are each calculated over a set of data bits in data memory channels 212-1 to 212-n”).
Regarding claim 6, the combination of Srinivasan in view of Lin, further in view of Lastras-Montano teaches the storage controller according to claim 5, wherein the pre-generated parity value is regenerated when the error bits are included in the parity area of the target data set (Srinivasan, col. 5, lines 65-67 through col. 6, lines 1-2, "When an uncorrectable error occurs, a set of parity bits associated with the data that was read from the memory channel is retrieved, and all data bits that were used to compute that set of parity bits are also retrieved").
Regarding claim 9, Srinivasan teaches a method of operating a storage controller that stores a target data set (Srinivasan, col. 11, lines 20-22, “process 900 can be performed by a host processor, an acceleration engine, a memory controller, or other components that can access the memory system”), the method comprising:
generating a plurality of parity values by matching each of a plurality of first bit combinations corresponding to the number of error bits to positions of the error bits (Srinivasan, Fig. 9, block 906, col. 11, lines 40-42, "At block 906, error correction bits based on the set of data bits stored at the source location can be computed. For example, each error correction bit can be computed from a different combination of a subset of the data bits"); and
determining a corrected bit combination among the plurality of first bit combinations by comparing each of the plurality of parity values with a pre-generated parity value corresponding to the target data set (Srinivasan, Fig. 9, block 918 & block 920, col. 11, lines 55-63, " At block 918, if it is determined that the set of data bits has a correctable error based on the comparison of the error correction bits with the previously stored error correction code (e.g., the location of the erroneous bit(s) can be identified using ECC), then the set of data bits can corrected based on the ECC comparison... at block 920, the corrected set of data bits can be outputted as output data").
Srinivasan fails to teach comparing a number of error bits included in the target data set with a first reference value; and according to a determination that the number of the error bits is less than the first reference value, and wherein determining the corrected bit combination comprises stopping determining the corrected bit combination except when there is only one parity value among the plurality of parity values, that is equal to the pre-generated parity value.
However, Lin teaches comparing a number of error bits included in the target data set with a first reference value (Lin, Fig. 5, step 340, col. 5, lines 16-17, "In step S340, the ECC engine 250 determines whether the quantity of the error bits of the read data is greater than n"); and
according to a determination that the number of the error bits is less than the first reference value (Lin , col. 5, lines 21-25, "when the quantity of the error bits of the read data is not greater than n, in step S360, the ECC engine 250 performs an error correction procedure on the read data).
Srinivasan and Lin are both considered to be analogous to the claimed invention because both are in the same field of improving the reliability of memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Srinivasan to incorporate the teachings of Lin by including the functionality of performing error correction procedures when the number of error bits are less than a threshold value.
The suggestion/motivation for doing so would be to determine if the error bits are correctable (Lin, col. 5, lines 10-12, “Therefore, when the quantity of the error bits is not greater than 3, the error bits may be corrected by the ECC engine 250”).
The combination of Srinivasan in view of Lin, taken singly or combined, fails to teach wherein determining the corrected bit combination comprises stopping determining the corrected bit combination except when there is only one parity value among the plurality of parity values, that is equal to the pre-generated parity value.
However, Lastras-Montano, in an analogous art teaches wherein determining the corrected bit combination comprises stopping determining the corrected bit combination (Lastras-Montano, Fig. 13, block 1316, para. [0069], lines 16-18, “At block 1316, the error is determined to be an uncorrectable error. In exemplary embodiments, the system operation will halt,”; para. [0067], lines 9-19, “The exemplary process in FIG. 13 implements an error handling policy that corrects an error only when: (1) exactly one chip [also referred to herein as a memory device] signature is the "all zeros" vector… Any other syndromes are trapped and correction is not attempted since this could result in mis-correction, with erroneous data being utilized” [shortened for brevity]) except when (Lastras-Montano, Fig. 13, blocks 1318 & 1320, para. [0070], lines 1-4, “If, at block 1318, it is determined that the trapping set does not contain the signature of any of the chips [i.e., the error is correctable], then block 1320 is performed to correct the error”) there is only one parity value among the plurality of parity values, that is equal to the pre-generated parity value (Lastras-Montano, Fig. 13, blocks 1314 & 1318, para. [0069], lines 4-8, “Next, block 1314 is performed to determine if the signature of exactly one chip is all zeros [i.e, if the error is a correctable error]. If the signature of exactly one chip is all zeros, then block 1318 is performed to determine if the signature of any chip is in the trapping set”).
Srinivasan, Lin, and Lastras-Montano are all considered to be analogous to the claimed invention because all three are in the same field of improving the reliability of memory systems.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified the combination of Srinivasan in view of Lin to incorporate the teachings of Lastras-Montano by including the functionality of stopping the determination of a corrected bit combination, unless there is a single parity value match to a pre-generated parity value.
The suggestion/motivation for doing so would be to prevent the mis-correction of data and the utilization of erroneous data (Lastras-Montano, para. [0067], lines 16-19, “Any other syndromes are trapped and correction is not attempted since this could result in mis-correction, with erroneous data being utilized”).
Claim 10 is a method with limitations similar to the storage controller of claim 2, and is rejected under the same rationale.
Claim 11 is a method with limitations similar to the storage controller of claim 3, and is rejected under the same rationale.
Claim 12 is a method with limitations similar to the storage controller of claim 4, and is rejected under the same rationale.
Regarding claim 15, the combination of Srinivasan in view of Lin teaches the method according to claim 9, further comprising:
detecting the error bits from the target data set (Lin, col. 3, lines 62-65, "In step S210, the memory controller 110 performs a verification operation on the to-be-written data 200 to determine whether the data bits include error bits and record information of the error bits"); and
comparing the number of error bits with the first reference value according to a determination that the error bits are included in data areas of the target data set (Lin, col. 4, 6-9, "In the present embodiment, a correction capability of the ECC engine 250 is 3 bits. In step S220, the memory controller 110 determines whether the quantity of the error bits is greater than the correction capability of the ECC engine 250").
It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to have modified Srinivasan to incorporate the teachings of Lin by including the functionality of error detection in the target data set and comparing the number of error bits with a reference value.
The suggestion/motivation for doing so would be to determine if the error bits are correctable (Lin, col. 5, lines 10-12, “Therefore, when the quantity of the error bits is not greater than 3, the error bits may be corrected by the ECC engine 250”).
Claim 16 is a method with limitations similar to the method of claim 6, and is rejected under the same rationale.
Allowable Subject Matter
Claims 7-8 and 13-14 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Andre et al. (US 9,575,125) teaches error detection based on parity/difference information.
Tate et al. (US 10,848,182) teaches LDPC decoding and early termination based on parity check subgroups satisfying a condition.
Graumann (US 11,086,716) teaches hard-decode exit conditions and decoder stopping logic.
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/G.V.B./Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112