Tech Center 4100 • Art Units: 2112 2824 4100
This examiner grants 92% of resolved cases
Grace Victoria Braden serves in Tech Center 4100 and Art Unit 2112, where she has 37 resolved cases. Her allowance rate is 91.9 percent, which suggests a favorable outlook for applicants. The median days to allowance is 721, reflecting an efficient timeline for reaching a grant.
The data indicates an interview lift of 11.1 percent. This is a meaningful increase, suggesting that interviews are an effective way to resolve any outstanding issues and secure an allowance. For the 37 resolved cases, the combination of a 91.9 percent allowance rate and an 11.1 percent lift highlights the benefits of direct examiner engagement.
Practitioners should note that the 721 median days to allowance provides a relatively quick path to patent issuance in Art Unit 2112. While the 91.9 percent allowance rate is already high, the 11.1 percent interview lift suggests that oral advocacy can still be a decisive factor in successful prosecution. These 37 resolved cases establish a clear pattern of efficiency and examiner accessibility.
| App # | Title | Status | Assignee |
|---|---|---|---|
| 19065734 | NON-VOLATILE MEMORY DEVICE CAPABLE OF DETECTING BONDING DEFECTS AND DEFECT DETECTION METHOD THEREOF | Non-Final OA | SAMSUNG ELECTRONICS CO., LTD. |
| 19047769 | DATA PROCESSING METHOD, APPARATUS, AND DEVICE | Non-Final OA | HUAWEI TECHNOLOGIES CO., LTD. |
| 18944637 | End-to-End Data Integrity in a Storage System | Final Rejection | Pure Storage, Inc. |
| 18970343 | POWER CONTROL FOR HYBRID AUTOMATIC REPEAT REQUEST | Non-Final OA | QUALCOMM Incorporated |
| 18790434 | SYSTEMS AND METHODS FOR EXTENDED LONG RANGE COMMUNICATION IN WIRELESS LOCAL AREA NETWORKS (WLANS) | Non-Final OA | Avago Technologies International Sales Pte. Limited |
| 19302257 | METHODS, APPARATUS AND SYSTEMS FOR REDUCED COMPLEXITY POLAR CODES BASED ON MODIFIED CYCLIC-REDUNDANCY-CHECK (CRC) PROCEDURES | Non-Final OA | InterDigital Patent Holdings, Inc. |
| 18597215 | HOLD TIME IMPROVED LOW AREA FLIP-FLOP ARCHITECTURE | Final Rejection | Texas Instruments Incorporated |
| 18668724 | DIE-TO-DIE INTERFACE USING SIMULTANEOUS BIDIRECTIONAL LINKS ON AN INTERPOSER | Non-Final OA | NVIDIA Corporation |
| 18948486 | INTEGRATED CIRCUIT AND MEMORY SYSTEM INCLUDING ECC CIRCUIT | Final Rejection | SK hynix Inc. |
| 18792301 | SEMICONDUCTOR DEVICE | Non-Final OA | SK hynix Inc. |
| 18762327 | TECHNIQUES FOR DATA PATH ADDRESS PROTECTION | Non-Final OA | Micron Technology, Inc. |
| 19176327 | Device and Method for Diagnosis of the Same | Non-Final OA | Taiwan Semiconductor Manufacturing Company, Ltd. |
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