Prosecution Insights
Last updated: May 29, 2026
Application No. 18/521,523

THERMAL ISOLATION FOR HARDWARE COMPONENT PACKAGE

Non-Final OA §102§103
Filed
Nov 28, 2023
Examiner
HAIDER, WASIUL
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Microsoft Technology Licensing, LLC
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
495 granted / 538 resolved
+24.0% vs TC avg
Moderate +6% lift
Without
With
+6.3%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 11m
Avg Prosecution
11 currently pending
Career history
554
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
87.3%
+47.3% vs TC avg
§102
2.4%
-37.6% vs TC avg
§112
3.0%
-37.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 538 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election with traverse of Species IV in the reply filed on 3/30/2026 is acknowledged. Claims 2-5,11-14 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to a nonelected claim, there being no allowable generic or linking claim. In addition, claim 19 is also withdrawn as it is not associated with the elected embodiment. Applicant timely traversed the restriction (election) requirement in the reply filed on 3/30/2026. The traversal was made on the ground of not having mutually exclusive characteristics between the species stated. The examiner disagrees. Species I Fig. 2 illustrates wire bond (208) going through the package enclosure (210). Species II Fig. 3 shows wire bonds (308A, 308B) going directly to substrate 306. Species III Fig. 4 shows temperature-sensitive hardware component 402 bottom surface completely covered by heat spreader but separated from substrate by thermal isolation (424A). Species IV Fig. 5 shows isolation trench (520A, 520B) going through the temperature-sensitive hardware component (502). Each of the embodiment contains limitation that is different from the others and requires separate search strategy causing a search burden. "Serious burden" is a technical term specifically defined in the MPEP. For purposes of the initial requirement, appropriate explanation of separate classification, or separate status in the art, or a different field of search as defined in MPEP § 808.02 may prima facie show a serious burden on the examiner. See MPEP § 803 part II. It is because of such situation the stated restriction is considered as proper. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 1. Claim(s) 1,6 is/are rejected under 35 U.S.C. 102a(1) as being anticipated by US 20230048566 A1 (Wakabayashi). Regarding claim 1, Wakabayashi shows (Fig. 21) a hardware component package (1, sensor device, para 270), comprising: PNG media_image1.png 432 682 media_image1.png Greyscale a temperature-sensitive hardware component (10, para 268) having a first surface (top) and a second surface (bottom) opposite from the first surface; a substrate (30, para 215) coupled with the temperature-sensitive hardware component via a wire bond (34, para 214) connected to the first surface of the temperature-sensitive hardware component; a package enclosure (40, para 270) coupled with the second surface of the temperature-sensitive hardware component (coupling via 20 and 30), the package enclosure including a central portion (41) and a lateral portion (44a) that is thermally coupled with the wire bond (thermal coupling via relay substrate 30 and bonding wire 34 and package substrate 40), the central portion and the lateral portion formed from separate pieces of material (46 made of metal and 40 made of ceramic) and separated by a thermal isolation layer at an interface between the central portion and the lateral portion (ceramic substrate separating the heat dissipation areas 46 and 44a); and a thermoelectric cooler (TEC) disposed (20, para 271) between the second surface of the temperature-sensitive hardware component and the package enclosure, the TEC contacting the central portion of the package enclosure, such that at least some heat generated by the temperature-sensitive hardware component is dissipated to the package enclosure via the TEC (para 272). Regarding claim 6, Wakabayashi shows (Fig. 21) wherein the temperature- sensitive hardware component (10) is an image sensor (para 48), wherein the image sensor includes a photodiode portion (pixel region 11, pixels made of photoelectric conversion unit 121, para 40) and an edge portion (10 portion surrounding 11), and wherein the wire bond (33) is connected to the edge portion of the image sensor. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 1. Claim(s) 7-9,15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakabayashi as applied to claim 6 above, further in view of US 20110089517 A1 (Venezia). Regarding claim 7, Wakabayashi shows wherein the image sensor, the edge portion and the photodiode portion. Wakabayashi does not show wherein the image sensor includes a thermal isolation trench between the edge portion and the photodiode portion to reduce heat transfer from the edge portion to the photodiode portion. Venezia shows (Figs. 2,6) wherein the image sensor (600, para 28) includes a thermal isolation trench (155 of insulated TSV 101, para 20,22) between the edge portion (125, Fig. 6) and the photodiode portion (115 F-6 or 200 F-2) to reduce heat transfer from the edge portion to the photodiode portion. It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Venezia, with thermal isolation trench, to the invention of Wakabayashi. The motivation to do so is that the combination produces the predictable result of thermal protection of the sensor region from the peripheral heating. Regarding claim 8, Wakabayashi in view of Venezia shows the image sensor includes a first layer (115, Venezia) separated from a second layer (151, Venezia) by a sensor thermal isolation layer (145, dielectric with low thermal conductivity, Venezia), and wherein the thermal isolation trench between the edge portion and the photodiode portion extends into the sensor thermal isolation layer (155,145, Venezia). Regarding claim 9, Wakabayashi in view of Venezia shows wherein the first layer of the image sensor (200, Venezia) is electrically coupled with the second layer via one or more conductive wires (Venezia, 130,140,101,160) extending between the first layer (115, Venezia) and the second layer (151, Venezia), through the sensor thermal isolation layer (Venezia, 145). Regarding claim 15, Wakabayashi shows (Fig. 21) an image sensor package (1, sensor device, para 270), comprising: an image sensor (para 48) having a first surface (top) and a second surface (bottom) opposite from the first surface, the image sensor including a photodiode portion (11 of 10) and an edge portion (area surrounding 11 in 10), a substrate (30, para 215) coupled with the image sensor via a wire bond (34, para 214) connected to the edge portion of the image sensor; a package enclosure (40, para 270) coupled with the second surface of the image sensor; and a thermoelectric cooler (TEC) (20, para 271) disposed between the second surface of the image sensor and the package enclosure, such that at least some heat generated by the image sensor is dissipated to the package enclosure via the TEC (para 272). Wakabayashi does not show the image sensor including a thermal isolation trench between the edge portion and the photodiode portion to reduce heat transfer from the edge portion to the photodiode portion. Venezia shows (Figs. 2,6) the image sensor including a thermal isolation trench (155 of insulated TSV 101, para 20,22) between the edge portion (125, Fig. 6) and the photodiode portion to reduce heat transfer from the edge portion to the photodiode portion (115 F-6 or 200 F-2). It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Venezia, with thermal isolation trench, to the invention of Wakabayashi. The motivation to do so is that the combination produces the predictable result of thermal protection of the sensor region from the peripheral heating. Regarding claim 16, Wakabayashi in view of Venezia shows wherein the package enclosure (Wakabayashi, 40, para 270) includes a central portion (Wakabayashi, 46, para 270) that contacts the TEC (Wakabayashi 20), a lateral portion (Wakabayashi 41b) that is thermally coupled with the wire bond (Wakabayashi 33) connected to the edge portion of the image sensor, and a thermal isolation layer (Venezia 155 of insulated TSV 101, para 20,22) at an interface between the central portion (Venezia 115 F-6 or 200 F-2) and the lateral portion (Venezia 125, Fig. 6), the thermal isolation layer having a lower thermal conductivity than the central portion and the lateral portion of the package enclosure. Regarding claim 17, Wakabayashi in view of Venezia shows wherein the package enclosure is an airtight package enclosure that separates a package atmosphere from an external atmosphere (Wakabayashi para 185). 2. Claim(s) 10,18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wakabayashi in view of Venezia as applied to claim 7 or 15 above, further in view of US 20230384543 A1 (Hsia). Regarding claim 10, Wakabayashi in view of Venezia shows the thermal isolation trench and the TEC. Wakabayashi in view of Venezia does not show wherein the thermal isolation trench extends into the TEC. Hsia shows (Fig. 18) the thermal isolation trench (dielectric trench for 88 and 92 through dielectric 36 and 60S, para 46) extends into the TEC (66, para 46). It would have been obvious to one of ordinary skill in the art, at or before the effective filing date of the invention was made, to add the invention of Hsia, with thermal isolation trench extends into the TEC, to the invention of Wakabayashi in view of Venezia. The motivation to do so is that the combination produces the predictable result of cooling of the photonic die region or sensor region (para 44). Regarding claim 18, the prior art/s as noted in the above rejection of claim 10, discloses the entire claimed invention. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to WASIUL HAIDER whose telephone number is (571)272-1554. The examiner can normally be reached M-F 9 a.m. - 6 p.m.. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /WASIUL HAIDER/Primary Examiner, Art Unit 2812
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Prosecution Timeline

Nov 28, 2023
Application Filed
Apr 17, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
98%
With Interview (+6.3%)
1y 11m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 538 resolved cases by this examiner. Grant probability derived from career allowance rate.

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