DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In response to an Office action mailed on 04/16/2026 (“04/16/2026 OA”), the Applicant amended independent claim 1 in a reply filed on 07/16/2026. Applicant’s amendments to independent claim 1 have substantively changed the scope of claim 1 and its respective dependent claims.
Currently, claims 1-16 are examined as below.
Response to Arguments
Applicant’s amendments to the title of the invention have overcome the specification objections as set forth under line item number 1 in the 04/16/2026 OA.
Applicant’s amendments to independent claim 1 have overcome the prior-art rejections as set forth under line item numbers 2-4- in the 04/16/2026 OA. Despite the Applicant’s substantive amendments, the previously-cited prior arts Lee and Xue still read on the claims. Details please see below.
New grounds of rejections under 35 U.S.C. 103 and 102(a)(1) are provided as follows.
I. Prior-art rejections based at least in part with Fig. 1A of Lee
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-16 are rejected under 35 U.S.C. 103 as being unpatentable over US 2016/0005747 A1 to Lee et al. (“Lee”) in view of US 2021/0296336 A1 to Xue et al. (“Xue”).
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Regarding independent claim 1, Lee in Figs. 1A and 4 teaches a memory device 1200 (Fig. 4 & ¶ 53, memory device 1200 has a structure as described in Fig. 1A; Fig. 1A & ¶ 21, the device in Fig. 1A includes a memory cell) comprising:
a stack structure 11/12 (Fig. 1A & ¶ 21, a collective of conductive layers 11 and insulating layers 12); and
a channel layer 14/15 (Fig. 1A & ¶ 29, first channel layer 14, 15) inside the stack structure 11/12,
wherein the channel layer 14/15 includes:
a first sub-channel layer 14 (Fig. 1A & ¶ 29, first channel layer 14);
a liner layer 16 (Fig. 1A & ¶ 30, liner layer 16) formed along an inner wall of the first sub-channel layer 14; and
a second sub-channel layer 15 (Fig. 1A & ¶ 29, first channel layer 15; ¶ 24, the first channel layer 15 includes silicon) formed along an inner wall of the liner layer 16; and
the liner layer 16 is between the first sub-channel layer 14 and the second sub-channel layer 15.
Lee does not explicitly disclose wherein the second sub-channel layer includes an impurity; and wherein the liner layer is between the first sub-channel layer and the impurity included in the second sub-channel layer.
Xue recognizes a need for providing a higher merging point for the channel structure to effectively reduce the risk of channel layer broken during process or treatment (¶ 45). Xue satisfies the need by providing a channel layer including a silicon layer (¶ 66, first channel layer 610 is a silicon layer) doped with an impurity (¶ 68 & ¶ 100, boron ions are implanted to the channel layer 610).
Before the effective filing date of the claimed invention, it would have been obvious to one of ordinary skill in the art to modify the second sub-channel layer taught by Lee with the boron ions as impurity taught by Xue, so as to provide a higher merging point for the channel structure to effectively reduce the risk of channel layer broken during process or treatment (Xue: ¶ 45).
Furthermore, the combination of Lee and Xue would disclose that the liner layer 16 is between the first sub-channel layer 14 and the impurity included in the second sub-channel layer 15 (Lee: Fig. 1A; Xue), as the second sub-channel layer 15 is doped with the impurity (Xue).
Regarding claim 2, Lee in Fig. 1A further teaches the first sub-channel layer 14 includes an undoped silicon layer (¶ 24).
Regarding claim 3, the combination of Lee and Xue further teaches the second sub-channel layer 15 includes a silicon layer (Lee: ¶ 24) doped with the impurity (Xue: ¶ 65, ¶ 100).
Regarding claim 4, the combination of Lee and Xue further teaches the impurity is a Group XIII element (Xue: ¶ 68 & ¶ 100, boron, which is a Group XIII element).
Regarding claim 5, the combination of Lee and Xue further teaches the impurity is boron (Xue: ¶ 68 & ¶ 100, boron).
Regarding claim 6, Lee in Fig. 1A further teaches the liner layer 16 is an insulating layer (¶ 25, liner layer 16 is an oxide layer, which is the same insulating material for the liner layer as the Applicant purported in paragraph 51 in the specification of the present application).
Regarding claim 7, Lee does not disclose the first sub-channel layer has a first width, and the second sub-channel layer has a second width less than the first width.
However, Lee teaches a general condition in which the first sub-channel layer 14 has a first width (Fig. 1A), and the second sub-channel layer 15 has a second width (Fig. 1A).
According to Section 2144.05 of the MPEP, "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F. 2d 454, 456, 105 USPQ 233, 235 (CCPA 1955).
Here, since Lee teaches said general conditions, it would not be inventive to discover the optimum or workable ranges by routine experimentation before the effective filing date of the claimed invention. Unless the Applicant can show that the specific conditions of the first sub-channel layer has a first width, and the second sub-channel layer has a second width less than the first width produce unexpected results that are different in kind and not different in degree, said general conditions taught by Lee renders claim 7 obvious.
Regarding claim 8, Lee in Fig. 1A further teaches the liner layer 16 has a third width less than the second width (Fig. 1A, width of the layer 15).
Regarding claim 9, Lee in Fig. 1A further teaches each of the first sub-channel layer 14, the second sub-channel layer 15, and the liner layer 16 penetrates the stack structure 11/12 (Fig. 1A).
Regarding claim 10, Lee in Fig. 1A further teaches the liner layer 16 is formed between the first sub-channel layer 14 and the second sub-channel layer 15 (Fig. 1A).
Regarding claim 11, Lee in Fig. 1A further teaches the liner layer 16 is formed along an outer wall of the second sub-channel layer 15 (Fig. 1A).
Regarding claim 12, Lee in Fig. 1A further teaches a memory layer 13 (Fig. 1A & ¶ 27, dielectric layer 13 is a memory layer of a memory cell) on an outer wall of the channel layer 14/15 (Fig. 1A).
Regarding claim 13, Lee in Fig. 1A further teaches the memory layer 13 includes a blocking layer 13A (Fig. 1A & ¶ 27, charge blocking layer 13A), a charge trap layer 13B (Fig. 1A & ¶ 27, data storage layer 13B, and the data storage layer is provided as a charge trap layer to store information1), and a tunnel insulating layer 13C (Fig. 1A & ¶ 27, tunnel insulating layer 13C).
Regarding claim 14, Lee in Fig. 1A further teaches the tunnel insulating layer 13C surrounds a side surface of the first sub-channel layer 14 (Fig. 1A),
the charge trap layer 13B surrounds a side surface of the tunnel insulating layer 13C (Fig. 1A), and
the blocking layer 13A surrounds a side surface of the charge trap layer 13B (Fig. 1A).
Regarding claim 15, Lee in Fig. 1A further teaches a pillar 16 (Fig. 1A & ¶ 16, liner layer 16 is in a form of a pillar interposed between (i.e., inside) the channel layers 14 and 15) inside the channel layer 14/15.
Regarding claim 16, Lee in Fig. 1A further teaches the stack structure 11/12 includes conductive layers 11 (¶ 20, conductive layer 11) alternately stacked with interlayer insulating layers (Fig. 1A, ¶ 20, insulating layer 12).
II. Prior-art rejections based on Fig. 2D of Lee
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee.
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Regarding independent claim 1, Lee in Figs. 1A, 2D and 4 teaches a memory device (Figs. 1A, 2D, 4 & ¶ 53, memory device 1200 has a structure as described in Figs. 1A and 2D; Fig. 2D & ¶ 33, the device in Fig. 2D includes memory cells) comprising:
a stack structure 22/28 (Fig. 2D, ¶ 40, a collective of second material layers 22 and conductive layer 28); and
a channel layer 24/25 (Figs. 1A, 2D, ¶ 29, ¶ 39, a collective of first semiconductor layer 24 and second semiconductor layer 25 of Fig. 2D, in which the firs semiconductor layer 24 corresponds to a channel layer 14 of Fig. 1A and the second semiconductor layer 25 corresponds to a channel layer 15 of Fig. 1A. In other words, the layers 24 and 25 are channel layers) inside the stack structure 22/28;
wherein the channel layer 24/25 includes:
a first sub-channel layer 24 (¶ 35, first semiconductor layer 24);
a liner layer 16 (Fig. 2A, ¶ 35, liner layer 26) formed along an inner wall of the first sub-channel layer 24; and
a second sub-channel layer 25 (Fig. 2D, ¶ 35, second semiconductor layer 25) formed along an inner wall of the liner layer 26;
wherein the second sub-channel layer 25 includes an impurity (¶ 36, the layer 25 is doped with impurities); and
wherein the liner layer 26 is between the first sub-channel layer 24 and the impurity included in the second sub-channel layer 25 (Fig. 2D, ¶ 36, since the layer 25 includes impurity, the liner layer 26 is between the layer 24 and impurity of the layer 25).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MIKKA LIU whose telephone number is (571)272-2568. The examiner can normally be reached on 9AM-5AM EST M-F.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos-Feliciano can be reached on 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/M.L./Examiner, Art Unit 2817
/ELISEO RAMOS FELICIANO/Supervisory Patent Examiner, Art Unit 2817
1 U.S. Patent Publication No. 2017/0330893 A1 to Han et al. discloses in paragraphs 105 and 108 that a data storage layer is a charge trap layer to store information in such a manner that a charge is trapped.
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