Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-19 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Claims 1 (and dependent claims 2-14) recite “A method for automatically performing maverick screening of semiconductor wafers, the method comprising: for each a plurality of die on a subject wafer, measuring a parameter of the die to obtain a measured parameter value; and comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer; and identifying the subject wafer as a maverick wafer if the deviation parameter value falls outside of a deviation tolerance.”
Claims 1-14, in view of the claim limitations, recite the abstract idea of “measuring a parameter of the die to obtain a measured parameter value; and comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer; and identifying the subject wafer as a maverick wafer if the deviation parameter value falls outside of a deviation tolerance.”
As a whole, in view of the claim limitations, but for the computer components and systems performing the claimed functions, the broadest reasonable interpretation of the recited “measuring a parameter of the die to obtain a measured parameter value; and comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer; and identifying the subject wafer as a maverick wafer if the deviation parameter value falls outside of a deviation tolerance.”; therefore, the claims recite mathematical concepts and mental processes. Accordingly, the claims recite a mathematical concept and a mental process, and thus, the claims recite an abstract idea under the first prong of Step 2A.
This judicial exception is not integrated into a practical application under the second prong of Step 2A. In particular, the claims recite the additional elements beyond the recited abstract idea of“[a] computer- implemented method” and “the method is carried out by one or more physical processors configured by machine-readable instructions” as recited in claims 15 and 19, individually and when viewed as an ordered combination, and pursuant to the broadest reasonable interpretation, each of the additional elements are computing elements recited at high level of generality implementing the abstract idea on a computer (i.e. apply it), and thus, are no more than applying the abstract idea with generic computer components such as such as collecting data, analyzing it using mathematical relationships, and reporting a result. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-14 and 16-18 do not integrate the abstract idea into a practical application because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception under Step 2B. As noted above, the aforementioned additional elements beyond the recited abstract idea, as an order combination, are no more than mere instructions to implement the idea using generic computer components (i.e. apply it), and further, generally link the abstract idea to a field of use, which is not sufficient to amount to significantly more than an abstract idea; therefore, the additional elements are not sufficient to amount to significantly more than an abstract idea. Additionally, these recitations as an ordered combination, simply append the abstract idea to recitations of generic computer structure performing generic computer functions are considered well-understood, routine, and conventional activities in the field of semiconductor testing and data analysis. Moreover, aside from the aforementioned additional elements, the remaining elements of dependent claims 2-14 and 16-18 do not transform the recited abstract idea into a patent eligible invention because these claims merely recite further limitations that provide no more than simply narrowing the recited abstract idea. Looking at these limitations as an ordered combination adds nothing additional that is sufficient to amount to significantly more than the recited abstract idea because they simply provide instructions to use a generic arrangement of generic computer components and recitations of generic computer structure that perform well-understood, routine, and conventional computer functions that are used to “apply” the recited abstract idea. There is no indication of a specialized machine, a non-conventional algorithm, a technological improvement and a transformation of an article into a different state. Thus, the elements of the claims, considered both individually and as an ordered combination, are not sufficient to ensure that the claim as a whole amounts to significantly more than the abstract idea itself. Since there are no limitations in these claims that transform the exception into a patent eligible application such that these claims amount to significantly more than the exception itself, claims 1-19 are rejected under 35 U.S.C. 101 as being directed to non-statutory subject matter.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of pre-AIA 35 U.S.C. 103(a) which forms the basis for all obviousness rejections set forth in this Office action:
(a) A patent may not be obtained though the invention is not identically disclosed or described as set forth in section 102, if the differences between the subject matter sought to be patented and the prior art are such that the subject matter as a whole would have been obvious at the time the invention was made to a person having ordinary skill in the art to which said subject matter pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-19 is/are rejected under pre-AIA 35 U.S.C. 103(a) as being unpatentable over Rathert et al (US 11,624,775) in view of Teplinsky et al (US 11,143,689).
Rathert et al disclose the following claimed features:
Regarding claim 1, a method for automatically performing maverick screening of semiconductor wafers (Figures 1-5), the method comprising: for each a plurality of die on a subject wafer, measuring (504) a parameter of the die to obtain a measured parameter value (column 20, lines 17-28); and identifying (508) the subject wafer as a maverick wafer if the deviation parameter value falls outside of a deviation tolerance (column 14, lines 34-46; column 20, line 48 to column 21, line 10).
Rathert et al disclose the claimed invention except for reciting comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer.
Teplinsky et al teach comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer (column 16, lines 7-29; column 18, lines 32-40).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to include comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer, as taught by Teplinsky et al into Rathert et al, for the purpose of improving defect detection accuracy and reducing false results.
Regarding claim 2, Rathert et al as modified by Teplinsky et al disclose wherein for each of at least some of the plurality of die, the deviation comprises a ratio between the measured parameter value and the expected parameter value (Rathert et al: column 16, line 37 to column 17, line 5).
Regarding claim 3, Rathert et al as modified by Teplinsky et al disclose the expected parameter value being a median of the measured parameter value of dies at the same position for the previously screened wafers (Rathert et al: column 6, lines 15-32).
Regarding claim 4, Rathert et al as modified by Teplinsky et al disclose the previously screened wafers being a most recent predetermined number of previously screened wafers (Rathert et al: column 8, lines 34-54).
Regarding claim 5, Rathert et al as modified by Teplinsky et al disclose for each of the plurality of die on the subject wafer, adjusting the expected parameter value of the parameter at the corresponding position for subsequent maverick wafer screening by adding the measured parameter value of the die to the history of measured parameter values for die at the corresponding position (Rathert et al: column 14, line 59 to column 15, line 19).
Regarding claim 6, Rathert et al as modified by Teplinsky et al disclose the deviation tolerance being a first deviation tolerance, the subject wafer being a first subject wafer, the method further comprising the following for a second subject wafer, the method further comprising: for each a plurality of die on a second subject wafer, measuring the parameter of the die to obtain a measured parameter value; and comparing the measured parameter value to the adjusted expected parameter value; calculating a deviation parameter value of the second subject wafer using the deviation value of the plurality of die of the second subject wafer; and identifying the second subject wafer as a maverick wafer if the deviation parameter value of the second subject wafer falls outside of the second deviation tolerance (Teplinsky et al: column 16, lines 7-29; column 18, lines 32-40).
Regarding claim 7, Rathert et al as modified by Teplinsky et al disclose the first subject wafer being identified as a maverick because the deviation parameter value of the first subject wafer fell outside of the first deviation tolerance, the second subject wafer not being identified as a maverick because the deviation parameter value of the second subject wafer fell inside of the second deviation tolerance (Rathert et al: column 24, lines 35-53).
Regarding claim 8, Rathert et al as modified by Teplinsky et al disclose the first deviation tolerance and the second deviation tolerance being the same (Rathert et al: column 24, lines 35-53).
Regarding claim 9, Rathert et al as modified by Teplinsky et al disclose the calculation of the deviation parameter value of the subject wafer being a median of the deviation values of the plurality of die on the subject water (Rathert et al: column 6, lines 15-32).
Regarding claim 10, Rathert et al as modified by Teplinsky et al disclose the parameter being a first parameter, the method further comprising the following for each of the plurality of die on the subject wafer: measuring a second parameter of the die to obtain a measured second parameter value; and comparing the measured second parameter value to an expected second parameter value, the expected second parameter value being dependent on a history of measured second parameter values of the second parameter of previous dies at a same position for the previously screened wafers, the comparison of the measured second parameter value to the expected second parameter value resulting in a second deviation between the second measured parameter value of the die and the expected second parameter value of the die (column 16, lines 7-29; column 18, lines 32-40).
Regarding claim 11, Rathert et al as modified by Teplinsky et al disclose each of the plurality of die containing a power transistor (TABLE 25; Figure 1; Teplinsky et al: column 32, lines 41-47).
Regarding claim 12, Rathert et al as modified by Teplinsky et al disclose the parameter being an on-resistance of the power transistor of the die (TABLE 25; Figure 1; Teplinsky et al: column 32, lines 41-47).
Regarding claim 13, Rathert et al as modified by Teplinsky et al disclose the parameter being a leakage current of the power transistor of the die (TABLE 25; Figure 1; Teplinsky et al: column 32, lines 41-47).
Regarding claim 14, Rathert et al as modified by Teplinsky et al disclose the plurality of die on the subject wafer comprising less that all of the die on the subject wafer (Rathert et al: column 16, lines 23-36).
Regarding claim 15, Rathert et al disclose a computer program product comprising one or more computer-readable media having thereon computer-executable instructions that, when executed by one or more processors of a computing system (column 18, line 56 to column 19, line 40), configure the computing system to automatically performing maverick screening of semiconductor wafers (Figures 1-5) by performing operations comprising: for each a plurality of die on a subject wafer, measuring (504) a parameter of the die to obtain a measured parameter value (column 20, lines 17-28); and identifying (508) the subject wafer as a maverick wafer if the deviation parameter value falls outside of a deviation tolerance (column 14, lines 34-46; column 20, line 48 to column 21, line 10).
Rathert et al disclose the claimed invention except for reciting comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer.
Teplinsky et al teach comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer (column 16, lines 7-29; column 18, lines 32-40).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to include comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer, as taught by Teplinsky et al into Rathert et al, for the purpose of improving defect detection accuracy and reducing false results.
Regarding claim 16, Rathert et al as modified by Teplinsky et al disclose the previously screened wafers being a most recent predetermined number of previously screened wafers (Rathert et al: column 8, lines 34-54).
Regarding claim 17, Rathert et al as modified by Teplinsky et al disclose the subject wafer being a first subject wafer, the method further comprising the following for a second subject wafer: for each of the plurality of die on the second subject wafer: adjusting the expected parameter value for the die at the corresponding position by adding the measured parameter value of the corresponding die of the first parameter value to the history of measured parameter values for die at the corresponding position; measuring a parameter of the die to obtain a measured parameter value; and comparing the measured parameter value to the adjusted expected parameter value; calculating a deviation parameter value of the second subject wafer using the deviation value of the plurality of die of the second subject wafer; and identifying the second subject wafer as a maverick wafer if the deviation parameter value of the second subject wafer falls outside of a deviation tolerance (Teplinsky et al: column 16, lines 7-29; column 18, lines 32-40).
Regarding claim 18, Rathert et al as modified by Teplinsky et al disclose the parameter being a first parameter, the method further comprising the following for each of the plurality of die on the subject wafer: measuring a second parameter of the die to obtain a measured second parameter value; and comparing the measured second parameter value to an expected second parameter value, the expected second parameter value being dependent on a history of measured second parameter values of the second parameter of previous dies at a same position for the previously screened wafers, the comparison of the measured second parameter value to the expected second parameter value resulting in a second deviation between the second measured parameter value of the die and the expected second parameter value of the die (Teplinsky et al: column 16, lines 7-29; column 18, lines 32-40).
Regarding claim 19, Rathert et al disclose a computing system comprising: one or more processors: one or more computer-readable media having thereon computer-executable instructions that, when executed by one or more processors of a computing system (column 18, line 56 to column 19, line 40), configure the computing system to automatically performing maverick screening of semiconductor wafers (Figures 1-5) by performing operations comprising: for each a plurality of die on a subject wafer, measuring (504) a parameter of the die to obtain a measured parameter value; and identifying (508) the subject wafer as a maverick wafer if the deviation parameter value falls outside of a deviation tolerance (column 14, lines 34-46; column 20, line 48 to column 21, line 10).
Rathert et al disclose the claimed invention except for reciting comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer.
Teplinsky et al teach comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer (column 16, lines 7-29; column 18, lines 32-40).
It would have been obvious to one having ordinary skill in the art at the time the invention was made to include comparing the measured parameter value to an expected parameter value, the expected parameter value being dependent on a history of measured parameter values of the parameter of previous dies at a same position as the die for previously screened wafers, the comparison resulting in a deviation between the measured parameter value of the die at the position and the expected parameter value of the die at the position; and calculating a deviation parameter value of the subject wafer using the deviation value of each of the plurality of die on the subject wafer, as taught by Teplinsky et al into Rathert et al, for the purpose of improving defect detection accuracy and reducing false results.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Lin et al (US 11,132,790) disclose a wafer map identification method that includes the following steps: obtaining a wafer map of at least one to-be-identified wafer; performing an image processing operation on the wafer map and a reference pattern, wherein the image processing operation includes: performing a convolution operation on the wafer map and the reference pattern respectively, extracting a critical feature of the wafer map after the convolution operation, and calculating a weight distribution based on the reference pattern after the convolution operation; and calculating a similarity between the processed wafer map and the processed reference pattern to identify the wafer map. Chang et al (US 9,435,847) disclose a method for testing a special pattern where a wafer is divided into multiple testing partitions, in which each of the testing partitions includes multiple dies. The dies in each testing partition of the wafer are respectively tested by multiple sites of the probe card to obtain a testing map. Then, a number of the dies having defects and a number of the dies without defect within each of the testing partitions in the testing map are accumulated to construct chi-square test and calculate a maximum P-value. Finally, it is determined whether a minimum of the maximum P-values of all of the testing partitions is smaller than a certain predetermined threshold. If the minimum is smaller than the threshold, it is determined that the testing map of the wafer contains the special pattern.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to AN H DO whose telephone number is (571)272-2143. The examiner can normally be reached on M-F 7:00am-4:00pm.
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/AN H DO/Primary Examiner, Art Unit 2853
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