DETAILED ACTION
Examiner’s Note
The prior arts cited in PTO-892 but not used in the current rejection are related to the claimed novelty and can also be used to reject the claims 1-22.
Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs, columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 and 12-22 are rejected under 35 U.S.C. 103 as being unpatentable over PARK et al. (US 20200058652 A1, hereinafter Park‘652) in view of Yang et al. (US 20200098858 A1, Yang‘858).
Regarding independent claim 1, Park‘652 teaches, “A chip (fig. 1-15; ¶ [0001] - ¶ [0076]), comprising:
a first active device (See annotated fig. 2A) having a first threshold voltage;
a second active device (See annotated fig. 2A) having a second threshold voltage, ((wherein the first threshold voltage is higher than the second threshold voltage)); and
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a bridge structure between the first active device and the second active device,
wherein the bridge structure comprises:
a first single diffusion break (SDB) (‘SDB’, see annotation);
a second SDB (‘SDB’, see annotation); and
a first diffusion region (see annotation) extending in a first direction between the first SDB and the second SDB”.
Regarding the limitataion, “wherein the first threshold voltage is higher than the second threshold voltage”, Park‘652 may not be explicitly discussing the threshold voltages of the first and second active devices.
However, Yang‘858 teaches the use of bridge structure comprising SDBs (304, fig. 3A-3C) between two transistors (G(1) and G(4)) requiring different threshold voltages (‘bias voltage’, ¶ [0044]).
Park‘652 and Yang‘858 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park‘652 with the features of Yang‘858 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Park‘652 and Yang‘858 to use the SDBs to isolate transistors of different threshold voltages according to the teachings of Yang‘858 with a general motivation of meeting the demand of reducing the size of silicon chips by integrating different semiconductor devices in a single chip and successfully isolate the devices from each other.
Regarding claim 2, “The chip of claim 1, wherein the first threshold voltage is at least 20 percent higher than the second threshold voltage”, Park‘652 modified with Yang‘858 teaches that the transistors work requiring different threshold voltages. While the cited prior art does not explicitly disclose the particular claimed value, the teachings therein would have led one of ordinary skill in the art at the time of invention to discover the claimed value during routine experimentation and optimization. The Applicant has not presented persuasive evidence that the claimed values are for a particular purpose that is critical to the overall claimed invention (i.e., the invention would not work without the specific claimed values). Also, the applicant has not shown that the claimed values produce a result that was new or unexpected enough to patentably distinguish the claimed invention over the cited prior art. Thus, because it has been held that where “the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation" (see MPEP 2144.05; In re Aller, 220 F.2d 454, 456, 105 USPQ 223, 225 (CCPA 1955)), it would have been obvious to add the claimed values to the rest of the claimed invention.
Regarding claim 3, Park‘652 modified with Yang‘858 further teaches, “wherein the first active device comprises: a second diffusion region (see annotated fig. 2A and fig. 1 of Park‘652 and 306P(1) in fig. 3A-3C of Yang‘858) extending in the first direction; and a first gate (G1 of Park‘652 and G(1) of Yang‘858) extending across the second diffusion region in a second direction perpendicular to the first direction”.
Regarding claim 4, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 3, wherein a distance between the first gate (G1, Park‘652) and the first SDB (SDB) in the first direction (‘first direction’) is approximately equal to a distance between the first SDB and the second SDB in the first direction (‘approximately’ is a broad limitataion in absence of any definition in the applicant’s specification)”.
Regarding claim 5, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 3, wherein a length of the first SDB (304 of Park‘652) in the first direction is approximately equal to a length of the first gate (G(1)) in the first direction (‘approximately’ is a broad limitataion in absence of any definition in the applicant’s specification)”.
Regarding claim 6, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 3, wherein the first SDB (¶ [0040], Park‘652 and ¶ [0060], Yang‘858) comprises an insulator disposed between an edge of the first diffusion region and an edge of the second diffusion region”.
Regarding claim 7, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 6, wherein the insulator comprises at least one of silicon nitride and silicon oxide (Silicon Nitride’, ¶ [0040], Park‘652).
Regarding claim 8, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 3, wherein the second active device comprises: a third diffusion region (306P(1) or 306P(2) on either side of the pair of SDBs can be associated with the second and third diffusion regions of Yang‘858, also see fig. 1, diffusion region on either side of DB1) extending in the first direction; and a second gate extending across the third diffusion region in the second direction”.
Regarding claim 9, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 8, wherein a distance between the first gate (G1, Park‘652) and the first SDB (SDB) in the first direction (‘first direction’) is approximately equal to a distance between the first SDB and the second SDB in the first direction, and the distance between the first SDB (SDB) and the second SDB in the first direction is approximately equal to a distance between the second SDB and the second gate (G2) in the first direction (‘approximately’ is a broad limitataion in absence of any definition in the applicant’s specification)”.
Regarding claim 12, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 8, wherein a length of the first SDB (304 of Park‘652) in the first direction and a length of the second SDB in the first direction are each approximately equal to a length of the first gate (G(1)) in the first direction (‘approximately’ is a broad limitataion in absence of any definition in the applicant’s specification)”.
Regarding claim 13, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 8, wherein the first SDB (¶ [0040], Park‘652 and ¶ [0060], Yang‘858) comprises a first insulator disposed between an edge of the second diffusion region and a first edge of the first diffusion region, and the second SDB comprises a second insulator disposed between a second edge of the first diffusion region and an edge of the third diffusion region”.
Regarding claim 14, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 13, wherein each of the first insulator and the second insulator comprises at least one of silicon nitride and silicon oxide (Silicon Nitride’, ¶ [0040], Park‘652).
Regarding claim 15, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 1, wherein the first active device comprises a first gate-all-around field-effect transistor (GAAFET) and the second active device comprises a second GAAFET (¶ [0048], Yang‘858)”.
Regarding claim 16, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 1, wherein the first active device comprises a first fin field-effect transistor (FinFET) and the second active device comprises a second FinFET (¶ [0003], ¶ [0016] etc, Yang‘858)”.
Regarding claim 17, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 1, further comprising: a third active device (fig. 1-2, Park‘652, G1 and F1 make at least four FinFET devices) having a third threshold voltage; and a fourth active device having a fourth threshold voltage, wherein the third threshold voltage is higher than the fourth threshold voltage (¶ [0044], Yang‘858), and the bridge structure is between the third active device and the fourth active device”.
Regarding claim 18, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 17, wherein each of the first active device and the second active device is an n-type active device, and each of the third active device and the fourth active device is a p-type active device (¶ [0033], Park‘652 and [0044], Yang‘858)”.
Regarding claim 19, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 17, wherein the bridge structure further comprises a second diffusion region extending in the first direction between the first SDB and the second SDB, and the second diffusion region is spaced apart from the first diffusion region in a second direction perpendicular to the first direction”.
Regarding claim 20, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 19, wherein the first active device and the third active device comprise: a third diffusion region extending in the first direction; a fourth diffusion region extending in the first direction, wherein the third diffusion region is spaced apart from the fourth diffusion region in the second direction; and gate extending across the third diffusion region and the fourth diffusion region in the second direction (fig. 1-2, Park‘652, G1 and F1 make at least four FinFET devices, also see fig. 3A, 3C of Yang‘858 for 3rd and fourth devices)”.
Regarding claim 21, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 20, wherein the third diffusion region is an n-type diffusion region, and the fourth diffusion region is a p-type diffusion region (¶ [0033], Park‘652 and [0044], Yang‘858)”.
Regarding claim 22, Park‘652 modified with Yang‘858 further teaches, “The chip of claim 20, wherein a distance between the gate (G1, Park‘652) and the first SDB (SDB) in the first direction is approximately equal to a distance between the first SDB and the second SDB in the first direction (‘approximately’ is a broad limitataion in absence of any definition in the applicant’s specification)”.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Park‘652 modified with Yang‘858 as applied to claim 8 as above, and further in view of BAEK et al. (US 20220246601 A1, hereinafter Baek‘601).
Regarding claim 10, Park‘652 modified with Yang‘858 teaches all the limitations described in claim 8.
But Park‘652 modified with Yang‘858 is silent upon the provision of wherein the first active device includes a first contact disposed on the second diffusion region between the first gate and the first SDB; the second active device includes a second contact disposed on the third diffusion region between the second SDB and the second gate; and the bridge structure comprises a third contact disposed on the first diffusion region between the first SDB and the second SDB, wherein the third contact is electrically floating.
However, Baek‘601 teaches a similar device (fig. 5A, ¶ [0065- ¶ [0066]]) the first active device includes a first contact (170) disposed on the second diffusion region between the first gate and the first SDB (150); the second active device includes a second contact (170_1) disposed on the third diffusion region between the second SDB (150) and the second gate; and the bridge structure comprises a third contact (170_2) disposed on the first diffusion region between the first SDB and the second SDB, wherein the third contact is electrically floating.
Park‘652 modified with Yang‘858 and Baek‘601 are analogous art because they both are directed to semiconductor devices and one of ordinary skill in the art would have had a reasonable expectation of success to modify Park‘652 modified with Yang‘858 with the features of Baek‘601 because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the invention to combine the teachings of Park‘652 modified with Yang‘858 and Baek‘601 to include contacts for transistor devices according to the teachings of Baek‘601 as these are conventional and essential components of the instant devices to connect to the other semiconductor devices in the circuits.
Regarding claim 11, Park‘652 modified with Yang‘858 and Baek‘601 further teaches, “The chip of claim 10, wherein the first contact, the second contact, and the third contact are formed from a same contact layer (Baek‘601, fig. 6, ¶ [0071])”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD M HOQUE whose telephone number is (571)272-6266 and email address is mohammad.hoque@uspto.gov. The examiner can normally be reached 9AM-7PM EST.
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/MOHAMMAD M HOQUE/Primary Examiner, Art Unit 2817
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