DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, claims 1-18, in the reply filed on March 23, 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Accordingly, claims 19 and 20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on March 23, 2026.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 2, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 2, and 5 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by deVilliers et al (US Pub 2021/0104609).
In re claim 1, deVilliers et al discloses a method for forming semiconductor interconnects, the method comprising: establishing a nanostructure in a substrate, wherein the nanostructure extends from a first semiconductor structure of the substrate to a second semiconductor structure of the substrate (i.e. 200); establishing an electrically conductive material on the substrate over the nanostructure to form a semiconductor assembly (i.e. 202); and performing a thermal process on the semiconductor assembly that causes the electrically conductive material to mold into the nanostructure established in the substrate to form an electrical interconnect that electrically connects the first semiconductor structure to the second semiconductor structure (i.e. 204 and 206; see at least paragraphs 0046-0047).
In re claim 2, deVilliers et al discloses wherein the nanostructure comprises a trench formed in the substrate (i.e. see at least paragraph 0027; Example 5).
In re claim 5, deVilliers et al discloses wherein establishing the nanostructure in the substrate comprises establishing the nanostructure in a silicon substrate, an oxide layer, or a dielectric layer (i.e. see at least paragraph 0023).
Allowable Subject Matter
Claims 3, 4, and 6-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHONY HO whose telephone number is (571)270-1432. The examiner can normally be reached 9AM - 5PM, Monday-Friday.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ANTHONY HO/Primary Examiner, Art Unit 2817