DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 1 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by Shah et al. (U.S. Patent No. 11,367,628).
Regarding to claim 1, Shah teaches a semiconductor chip, comprising:
a plurality of metal pads provided on a first surface of the semiconductor chip and defining a first area (Figs. 1-2, element 140; column 4, line 51);
a plurality of bumps provided on the plurality of metal pads (Figs. 1-2, element 145/155; column 5, lines 3-4); and
a friction structure provided around at least a portion of the first area near a corner of the first surface (Figs. 1-2, element 130; column 4, line 22-23).
Claims 1-11 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kaneko (U.S. Patent Application Publication No. 2010/0139962).
Regarding to claim 1, Kaneko teaches a semiconductor chip (Fig. 2, element 30), comprising:
a plurality of metal pads provided on a first surface of the semiconductor chip and defining a first area (Fig. 2, elements 11P, plurality of metal pads 11P provided on a surface of semiconductor chip and defining a first area);
a plurality of bumps provided on the plurality of metal pads (Fig. 2, elements 32); and
a friction structure provided around at least a portion of the first area near a corner of the first surface (Fig. 2, friction structure comprises groove DM1 and the edge barrier).
Regarding to claim 2, Kaneko teaches
the semiconductor chip comprises a device layer and an insulation layer (Fig. 2, semiconductor chip comprises device layer 31 and an insulation layer 12); and
the friction structure is formed of a same material as the insulation layer (Fig. 2).
Regarding to claim 3, Kaneko teaches the friction structure is a groove formed in the insulation layer (Fig. 2, [0040], lines 1-5, the friction structure is groove DM1 formed in the insulation layer 12).
Regarding to claim 4, Kaneko teaches the groove comprises two straight portions having end portions that meet near the corner of the insulation layer (Fig. 2).
Regarding to claim 5, Kaneko teaches the groove comprises a curved portion ([0040], line 5, annular shape means comprises a curved portion).
Regarding to claim 6, Kaneko teaches the friction structure is a barrier formed of the same material as the insulation layer (Fig. 2, [0040], line 5).
Regarding to claim 7, Kaneko teaches the friction structure is a barrier formed of the same material as the insulation layer (Fig. 2).
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Regarding to claim 8, Kaneko teaches the insulation layer defines a region in which the plurality of metal pads are provided and a region defining the barrier (Fig. 2, the insulation layer 12 defines a region in which the plurality of metal pads 11P are provided and a region defining the barrier at the edges).
Regarding to claim 9, Kaneko teaches the barrier comprises two straight portions having end portions that meet near the corner of the insulation layer (Fig. 2).
Regarding to claim 10, Kaneko teaches the barrier comprises a curved portion ([0040], line 5, annular shape means comprises a curved portion).
Regarding to claim 11, Kaneko teaches the insulation layer defines a region in which the plurality of metal pads are provided and a region defining a plurality of barriers, including the barrier, near each corner of the first surface (Fig. 2).
Claims 12 and 19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (U.S. Patent No. 8,928,132).
Regarding to claim 12, Tsai teaches a semiconductor package, comprising:
a top semiconductor chip (Fig. 22, element 200) comprising a first surface, a plurality of first metal pads provided on the first surface (Fig. 22, element 214), a plurality of first bumps provided on the plurality of first metal pads (Fig. 22, element 280), and a friction structure provided around at least a portion of the plurality of first metal pads near a corner of the first surface (Fig. 22, element 170);
a bottom semiconductor chip (Fig. 22, element 120) comprising an upper surface, a plurality of second metal pads provided on the upper surface facing the first surface of the top semiconductor chip (Fig. 22, element 270) and electrically connected to the plurality of first bumps of the top semiconductor chip (Fig. 22, element 280), a through-silicon via TSV electrically connected to at least some of the plurality of second metal pads (Fig. 22, elements 122; column 8, line 7), a plurality of third metal pads provided on a lower surface opposite to the upper surface (Fig. 22, element 123), and a plurality of second bumps provided on the plurality of third metal pads (Fig. 22, element 128); and
a non-conductive film material in a space between the top semiconductor chip and the bottom semiconductor chip (Fig. 22, element 150).
Regarding to claim 19, Tsai teaches a manufacturing method of a semiconductor package (Fig. 22, please view the figure upside down, the claimed bottom semiconductor chip is the top chip in the figure, and the claimed top semiconductor chip is the bottom chip in the figure), comprising:
providing a first redistribution layer on a first surface of a top semiconductor chip, wherein the first redistribution layer includes at least one of a groove or a barrier near a corner of the first surface (Fig. 19, first redistribution layer 150/126/125 on a first surface of a top semiconductor chip 121, the first redistribution layer includes groove or a barrier 150 near a corner of the first surface);
providing a plurality of bumps on the first redistribution layer (Fig. 19, element 270);
disposing a non-conductive film material on the first surface (Fig. 19, element 124);
aligning the first surface of the top semiconductor chip to face an upper surface of a bottom semiconductor chip (Fig. 20, element 200);
heating and pressing the top semiconductor chip toward the bottom semiconductor chip, melting the non-conductive film material and electrically connecting the plurality of bumps to metal pads provided on an upper surface of the bottom semiconductor chip (Fig. 21, heating and pressing fuses bumps 270 and 280 together); and
covering a side surface of the top semiconductor chip and the upper surface of the bottom semiconductor chip in a mold material (Fig. 22, covering a side surface of the top semiconductor chip 120 and the upper surface of the bottom semiconductor chip 200 in mold material 170).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 12-15 and 17-18 are rejected under 35 U.S.C. 103 as being unpatentable over Yu et al. (U.S. Patent No. 12,347,785) in view of Kaneko (U.S. Patent Application Publication No. 2010/0139962).
Regarding to claim 12, Yu teaches a semiconductor package, comprising:
a top semiconductor chip comprising a first surface, a plurality of first metal pads provided on the first surface, a plurality of first bumps provided on the plurality of first metal pads (Fig. 29, please see annotations in the attached figure);
a bottom semiconductor chip comprising an upper surface, a plurality of second metal pads provided on the upper surface facing the first surface of the top semiconductor chip and electrically connected to the plurality of first bumps of the top semiconductor chip, a through-silicon via TSV electrically connected to at least some of the plurality of second metal pads, a plurality of third metal pads provided on a lower surface opposite to the upper surface, and a plurality of second bumps provided on the plurality of third metal pads (Fig. 29, please see annotations in the attached figure); and
a non-conductive film material in a space between the top semiconductor chip and the bottom semiconductor chip (Fig. 29, please see annotations in the attached figure).
Yu does not disclose a friction structure provided around at least a portion of the plurality of first metal pads near a corner of the first surface.
Kaneko discloses a friction structure provided around at least a portion of the plurality of first metal pads near a corner of the first surface (Fig. 2, friction structure comprises groove DM1 and the edge barrier). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu in view of Kaneko to provide a friction structure around at least a portion of the plurality of first metal pads near a corner of the first surface in order to increase adhesion between the chips.
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Regarding to claim 13, Yu teaches the top semiconductor chip comprises a device layer and a first redistribution layer (Fig. 29, please see annotations in the attached figure). Yu as modified in view of Kaneko results in forming the friction structure. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Yu and Kaneko to form the friction structure with a same material as the first redistribution layer in order to simplify the fabrication process.
Regarding to claim 14, Kaneko discloses the friction structure is a groove, and a portion of the non-conductive film material is disposed in the groove (Fig. 2).
Regarding to claim 15, Kaneko discloses the friction structure is a barrier, a portion of the non-conductive film material surrounds the barrier (Fig. 2).
Regarding to claim 17, Yu teaches
the bottom semiconductor chip comprises a device layer and a second redistribution layer provided on the upper surface (Fig. 29, please see annotations in the attached figure); and
a portion of the second redistribution layer forms a bar (Fig. 29, please see annotations in the attached figure),
wherein the bar is disposed along at least a lateral side of the top semiconductor chip around a region to which the top semiconductor chip is attached (Fig. 29, please see annotations in the attached figure), and
the non-conductive film material is disposed internal to the bar at a later side of the top semiconductor chip (Fig. 29, please see annotations in the attached figure).
Regarding to claim 18, Yu teaches
a mold material configured to cover a side surface of the top semiconductor chip and an upper surface of the bottom semiconductor chip (Fig. 29, element 140A);
a package substrate attached to a lower surface of the bottom semiconductor chip (Fig. 29, element 180);
an under-fill disposed between the bottom semiconductor chip and the package substrate (Fig. 29, element 170); and
a plurality of third bumps provided on a lower surface of the package substrate (Fig. 29, element 190).
Allowable Subject Matter
Claims 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 16, the prior art fails to anticipate or render obvious the claimed limitations including “a trench in the second redistribution layer, wherein the trench is disposed along at least a lateral side of the top semiconductor chip around a region to which the top semiconductor chip is attached, and a portion of the non-conductive film material is disposed in the trench” in combination with the limitations recited in claim 12 and the rest of limitations recited in claim 16.
Regarding to claim 20, the prior art fails to anticipate or render obvious the claimed limitations including “providing a second redistribution layer on the upper surface of the bottom semiconductor chip; and forming at least one of a trench or a bar in the second redistribution layer and provided along at least a lateral side of the top semiconductor chip around a region to which the top semiconductor chip is attached” in combination with the limitations recited in claim 19.
Pertinent Art
For the benefits of the Applicant, US-20230387075-A1, US-12418005-B2, US-9997552-B2, US-11917756-B2, US-12451417-B2, US-20230402429-A1, US-12388041-B2, US-11296032-B2, and US-8143110-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose the combination of limitation including “a plurality of first bumps provided on the plurality of first metal pads, and a friction structure provided around at least a portion of the plurality of first metal pads near a corner of the first surface; a bottom semiconductor chip comprising an upper surface, a through-silicon via TSV electrically connected to at least some of the plurality of second metal pads.”
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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