DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Acknowledgment is made that applicant's Amendment, filed on July 10th, 2026, has been entered.
Upon entrance of the Amendment, claims 1, 3, 7, 8, 11, 12, and 16-20 were amended. Claims 1-20 are currently pending.
Response to Arguments
Applicant’s arguments with respect to claims 1 and 12 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Regarding to amended claim 19, Choi still discloses the amended features of the claim. Please see the figures with annotations below.
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Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 6-9, and 11-18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fuentes (U.S. Patent No. 8,982,577).
Regarding to claim 1, Fuentes teaches a semiconductor chip, comprising:
a plurality of metal pads (Fig. 6, elements 448) disposed on a first surface of the semiconductor chip (Fig. 6, element 102; column 6, lines 4-5) and defining a first area (Fig. 6);
a plurality of bumps disposed on the plurality of metal pads (Fig. 6, elements 450); and
a friction structure extending from the first surface of the semiconductor chip and disposed around at least a portion of the first area near a corner of the first surface (Fig. 6, groove/barrier structure 126/112 formed in portion of passivation layer 112).
Regarding to claim 2, Fuentes teaches
the semiconductor chip comprises a device layer and an insulation layer (Fig. 6, stack 102/112); and
the friction structure is formed of a same material as the insulation layer (Fig. 6, friction structure is formed from a portion of the insulation layer 112).
Regarding to claim 3, Fuentes teaches friction structure formed includes a groove extending in the insulation layer (Fig. 6, groove 126 extending in the insulation layer 112).
Regarding to claim 4, Fuentes teaches the groove comprises two straight portions having end portions that meet near the corner of the insulation layer (Fig. 6, the outer two grooves).
Regarding to claim 6, Fuentes teaches the friction structure comprises a plurality of grooves near each corner of the first surface (Fig. 6).
Regarding to claim 7, Fuentes teaches the friction structure includes a barrier formed of the same material as the insulation layer (Fig. 6, portion of the insulation layer 112 surrounding the groove).
Regarding to claim 8, Fuentes teaches the insulation layer defines a region in which the plurality of metal pads are disposed (Fig. 6, portion of layer 112 under chip 130) and a region defining the barrier (Fig. 6, portion of layer 112 surrounding the groove 126).
Regarding to claim 9, Fuentes teaches the barrier comprises two straight portions having end portions that meet near the corner of the insulation layer (Fig. 6, the outer two barriers).
Regarding to claim 11, Fuentes teaches the insulation layer defines a region in which the plurality of metal pads are provided disposed (Fig. 6, portion of layer 112 under chip 130) and a region defining a plurality of barriers, including the barrier, near each corner of the first surface (Fig. 6, portion of layer 112 surrounding the groove 126).
Regarding to claim 12, Fuentes teaches a semiconductor package, comprising:
a top semiconductor chip comprising a first surface (Fig. 6, element 130), a plurality of first metal pads disposed on the first surface (Fig. 6, elements 146), a plurality of first bumps disposed on the plurality of first metal pads (Fig. 6, elements 450), and a friction structure extending from the first surface provided around at least a portion of the plurality of first metal pads near a corner of the first surface (Fig. 6, element 112);
a bottom semiconductor chip comprising an upper surface (Fig. 6, element 102; column 6, lines 4-5), a plurality of second metal pads disposed provided on the upper surface facing the first surface of the top semiconductor chip and electrically connected to the plurality of first bumps of the top semiconductor chip (Fig. 6, elements 448), a through-silicon via TSV electrically connected to at least some of the plurality of second metal pads (Fig. 6, elements 110), a plurality of third metal pads disposed on a lower surface opposite to the upper surface (Fig. 6, elements 120), and a plurality of second bumps disposed on the plurality of third metal pads (bumps later connected to pads 120 to connect to external board); and
a non-conductive film material disposed between the top semiconductor chip and the bottom semiconductor chip to cover the plurality of first bumps (Fig. 6, element 654) and the friction structure and extending to an edge of the top semiconductor chip (Fig. 6).
Regarding to claim 13, Fuentes teaches the top semiconductor chip comprises a device layer (Fig. 6, element 102) and a first redistribution layer (Fig. 6, element 118); and the friction structure is formed of a same material as the first redistribution layer (Fig. 6, friction structure is formed from a portion of the insulation layer 112).
Regarding to claim 14, Fuentes teaches the friction structure is a groove (Fig. 6, groove 126 extending in the insulation layer 112), and a portion of the non-conductive film material is disposed in the groove (Fig. 6, portion of the non-conductive film material 654 is disposed in groove 126).
Regarding to claim 15, Fuentes teaches the friction structure is a barrier (Fig. 6, portion of the insulation layer 112 surrounding the groove), a portion of the non-conductive film material surrounds the barrier (portion of the non-conductive film material 654 surrounds the barrier).
Regarding to claim 16, Fuentes teaches
the bottom semiconductor chip comprises a device layer (Fig. 6, element 102) and a second redistribution layer disposed on the upper surface (Fig. 6, element including dielectric 112 and conductor 118); and
a trench in the second redistribution layer (Fig. 6, element 126),
wherein the trench is disposed along at least a lateral side of the top semiconductor chip around a region to which the top semiconductor chip is attached (Fig. 6), and
a portion of the non-conductive film material is disposed in the trench (Fig. 6, element 654).
Regarding to claim 17, Fuentes teaches
the bottom semiconductor chip comprises a device layer (Fig. 6, element 102) and a second redistribution layer disposed on the upper surface (Fig. 6, element 118); and
a portion of the second redistribution layer forms a bar (Fig. 6,),
wherein the bar is disposed along at least a lateral side of the top semiconductor chip around a region to which the top semiconductor chip is attached (Fig. 6), and
the non-conductive film material is disposed internal to the bar at the lateral side of the top semiconductor chip (Fig. 6, element 654).
Regarding to claim 18, Fuentes teaches
a mold material configured to cover a side surface of the top semiconductor chip and an upper surface of the bottom semiconductor chip (Fig. 6, element 148, similar to which shown in Fig. 5);
a package substrate attached to a lower surface of the bottom semiconductor chip (Fig. 6, element 108);
an under-fill disposed between the bottom semiconductor chip and the package substrate (Fig. 6, element 654); and
a plurality of third bumps provided disposed on a lower surface of the package substrate (bumps later connected to pads 120 to connect to external board).
Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Choi et al. (U.S. Patent No. 8,928,132).
Regarding to claim 19, Tsai teaches a manufacturing method of a semiconductor package (Fig. 22, please view the figure upside down, the claimed bottom semiconductor chip is the top chip in the figure, and the claimed top semiconductor chip is the bottom chip in the figure), comprising:
forming a first redistribution layer on a first surface of a top semiconductor chip, wherein the first redistribution layer includes at least one of a groove or a barrier near a corner of the first surface (Fig. 19, first redistribution layer 150/126/125 on a first surface of a top semiconductor chip 121, the first redistribution layer includes groove or a barrier 150 near a corner of the first surface);
forming a plurality of bumps on the first redistribution layer (Fig. 19, element 270);
disposing a non-conductive film material on the first surface (Fig. 19, element 124);
aligning the first surface of the top semiconductor chip to face an upper surface of a bottom semiconductor chip (Fig. 20, element 200);
heating and pressing the top semiconductor chip toward the bottom semiconductor chip, melting the non-conductive film material such that the non-conductive film material contacts a sidewall of the groove or the barrier and electrically connecting the plurality of bumps to metal pads formed on an upper surface of the bottom semiconductor chip (Fig. 21, heating and pressing fuses bumps 270 and 280 together); and
covering a side surface of the top semiconductor chip and the upper surface of the bottom semiconductor chip in a mold material (Fig. 22, covering a side surface of the top semiconductor chip 120 and the upper surface of the bottom semiconductor chip 200 in mold material 170).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Fuentes (U.S. Patent No. 8,982,577), as applied to claims 1-3 above, in view of Takano (U.S. Patent No. 7,157,308).
Regarding to claim 5, Fuentes does not disclose the groove comprises a curved portion. Takano discloses a groove comprises a curved portion (Fig. 5(c)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fuente in view of Takano to comprise a curved portion in the groove in order to prevent forming of voids when filling.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Fuentes (U.S. Patent No. 8,982,577), as applied to claims 1-2 and 7-8 above, in view of Takano (U.S. Patent No. 7,157,308).
Regarding to claim 10, Fuentes does not disclose the barrier comprises a curved portion. Takano discloses a barrier comprises a curved portion (Fig. 5(c)). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fuente in view of Takano to comprise a curved portion in the barrier in order to prevent forming of voids when filling.
Allowable Subject Matter
Claim 20 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter:
Regarding to claim 20, the prior art fails to anticipate or render obvious the claimed limitations including “forming a second redistribution layer on the upper surface of the bottom semiconductor chip; and forming at least one of a trench or a bar in the second redistribution layer and formed along at least a lateral side of the top semiconductor chip around a region to which the top semiconductor chip is attached” in combination with the limitations recited in claim 19.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/VU A VU/Primary Examiner, Art Unit 2897
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