DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 and 18 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
For the above mentioned reasons, the rejection is deemed proper and considered final.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-3, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sato (US 2016/0276281; hereinafter Sato).
Regarding claim 1, Fig 7 of Sato discloses an interconnect structure comprising:
a first dielectric layer (25; Fig 7; ¶ [0048]) including a trench (25a; Fig 7; ¶ [0044]);
a first conductive layer (26a; Fig 7; ¶ [0056]) in the trench (25a; Fig 7; ¶ [0044]), the first conductive layer (26a; Fig 7; ¶ [0056]) including a plurality of first graphene layers (26a; Fig 7; ¶ [0056]) stacked in a direction from an inner surface of the trench toward a center of the trench (Fig 7);
a second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) on the first dielectric layer (25; Fig 7; ¶ [0048]), the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) including a through hole (34a/31a; Fig 7; ¶ [0068]-[0069]) extending to the trench (25a; Fig 7; ¶ [0044]); and
a second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) in the through hole (34a/31a; Fig 7; ¶ [0068]-[0069]), wherein the plurality of first graphene layers (26a; Fig 7; ¶ [0056]) extend from the inner surface of the trench (25a; Fig 7; ¶ [0044]) and fill the trench occupying at least a majority of the trench (Fig 7).
Regarding claim 2, Fig 7 of Sato discloses the second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) comprises a plurality of second graphene layers (35a; Fig 7; ¶ [0068]-[0069]).
Regarding claim 3, Fig 7 of Sato discloses the second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) comprises a metal material (42b; Fig 7; ¶ [0068]-[0069]).
Regarding claim 18, Fig 7 of Sato discloses an electronic device comprising:
a substrate (11; Fig 7; ¶ [0026]); and
an interconnect structure on the substrate,
wherein the interconnect structure includes:
a first dielectric layer (25; Fig 7; ¶ [0048]) including a trench (25a; Fig 7; ¶ [0044]);
a first conductive layer (26a; Fig 7; ¶ [0056]) in the trench (25a; Fig 7; ¶ [0044]), the first conductive layer (26a; Fig 7; ¶ [0056]) including a plurality of first graphene layers (26a; Fig 7; ¶ [0056]) stacked in a direction from an inner surface of the trench toward a center of the trench (Fig 7);
a second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) on the first dielectric layer (25; Fig 7; ¶ [0048]), and
a second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]),
wherein the first conductive layer (26a; Fig 7; ¶ [0056]) including a plurality of first graphene layers (26a; Fig 7; ¶ [0056]) stacked in a direction from an inner surface of the trench toward a center of the trench (Fig 7), the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) includes a through hole (34a/31a; Fig 7; ¶ [0068]-[0069]) extending to the trench (25a; Fig 7; ¶ [0044]) and the second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) is in the through hole (34a/31a; Fig 7; ¶ [0068]-[0069])
wherein the plurality of first graphene layers (26a; Fig 7; ¶ [0056]) extend from the inner surface of the trench (25a; Fig 7; ¶ [0044]) and fill the trench occupying at least a majority of the trench (Fig 7).
Regarding claim 19, Fig 7 of Sato discloses the second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) comprises a plurality of second graphene layers (35a; Fig 7; ¶ [0068]-[0069]).
Regarding claim 20, Fig 7 of Sato discloses a third dielectric layer (34; Fig 7; ¶ [0068]-[0069]) on the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]),
wherein the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) and the third dielectric layer (34; Fig 7; ¶ [0068]-[0069]) define the through hole (34a/31a; Fig 7; ¶ [0068]-[0069]) such that the through hole extends through the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) to the third dielectric layer (34; Fig 7; ¶ [0068]-[0069]) and penetrates through the third dielectric layer (34; Fig 7; ¶ [0068]-[0069]), and
the second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) fills the through hole.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 4-6 are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2016/0276281; hereinafter Sato) as applied to claim 1 and further in view of Saito et al (US 2017/0062345; hereinafter Saito).
Regarding claim 4, Sato does not expressly disclose the first conductive layer further comprises a metal material contacting the inner surface of the trench.
In the same field of endeavor, Fig 2 of Saito discloses a first conductive layer (23a/21a/22a; Fig 2; ¶ [0027]) comprises a metal material (21a; Fig 2; ¶ [0032]) contacting the inner surface of a trench (14a; Fig 2; ¶ [0032]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the first conductive layer further comprises a metal material contacting the inner surface of the trench as the metal material are adhesive layers and also does not easily change the band structure of the graphene sheets (¶ [0032]).
Regarding claim 5, Fig 7 of Sato discloses the second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) comprises a plurality of second graphene layers (35a; Fig 7; ¶ [0068]-[0069]).
Regarding claim 6, Fig 7 of Sato discloses the second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) comprises a metal material (42b; Fig 7; ¶ [0068]-[0069]).
Claim(s) 7-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2016/0276281; hereinafter Sato) as applied to claim 1 and further in view of Kiyomura et al (US 2009/0072329; hereinafter Kiyomura).
Regarding claim 7, Sato discloses the first dielectric layer (25; Fig 7; ¶ [0048]) comprises a dielectric material such as silicon oxide (¶ [0048]).
However Sato does not expressly disclose the dielectric constant of 3.6 or less.
In the same field of endeavor, Kiyomura discloses dielectric constant of silicon oxide is 3.6 (¶ [0106]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the first dielectric layer comprises a dielectric material such as silicon oxide and having the dielectric constant of 3.6 or less as it is well known in the art that the silicon oxide has a dielectric constant within the claimed range (¶ [0106]).
Regarding claim 8, Fig 7 of Sato discloses the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) comprises a dielectric material that is selectively depositable on the first dielectric layer.
Regarding claim 9, Fig 7 of Sato discloses a third dielectric layer (34; Fig 7; ¶ [0068]-[0069]) on the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]),
wherein the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) and the third dielectric layer (34; Fig 7; ¶ [0068]-[0069]) define the through hole (34a/31a; Fig 7; ¶ [0068]-[0069]) such that the through hole extends through the second dielectric layer (31; Fig 7; ¶ [0068]-[0069]) to the third dielectric layer (34; Fig 7; ¶ [0068]-[0069]) and penetrates through the third dielectric layer (34; Fig 7; ¶ [0068]-[0069]), and
the second conductive layer (35a/42b; Fig 7; ¶ [0068]-[0069]) fills the through hole.
Regarding claim 10, Sato discloses the third dielectric layer (34; Fig 7; ¶ [0068]-[0069]) comprises a dielectric material such as silicon oxide (¶ [0048]).
However Sato does not expressly disclose the dielectric constant of 3.6 or less.
In the same field of endeavor, Kiyomura discloses dielectric constant of silicon oxide is 3.6 (¶ [0106]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the third dielectric layer comprises a dielectric material such as silicon oxide and having the dielectric constant of 3.6 or less as it is well known in the art that the silicon oxide has a dielectric constant within the claimed range (¶ [0106]).
Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2016/0276281; hereinafter Sato) as applied to claim 1 and further in view of Kuo et al (US 2019/0006230; hereinafter Kuo).
Regarding claim 11, Sato does not expressly disclose a width of the trench is equal to or less than 10 nm.
In the same field of endeavor, Fig 1B of Kuo discloses a width of a trench (107; Fig 1B) is equal to 5 nm (¶ [0029]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a width of a trench in the interconnects is within the claimed range in order to control the aspect ratio of the trench (¶ [0029]).
Claim(s) 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Sato (US 2016/0276281; hereinafter Sato) as applied to claim 1 and further in view of Shin et al (US 2021/0355582; hereinafter Shin).
Regarding claim 12, Sato does not expressly disclose the plurality of first graphene layers comprise intrinsic graphene or nanocrystalline graphene.
In the same field of endeavor, Shin discloses graphene layers can comprise nanocrystalline graphene (¶ [0062]).
Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the graphene layers comprises nanocrystalline graphene in order to form the graphene layer having a nano- level grain size which is less than those of the general crystalline graphene (¶ [0067]).
Regarding claim 13, Sato in view of Shin as modified above in claim 12 discloses the nanocrystalline graphene (¶ [0062] of Shin) comprises crystals having a size of about 0.5 nm to about 200 nm (¶ [0067] of Shin).
Regarding claim 14, Sato in view of Shin as modified above in claim 12 discloses in the nanocrystalline graphene a ratio of carbons having an sp2 bond structure to total carbons is about 50% to about 99% (¶ [0067] of Shin).
Regarding claim 15, Barth in view of Shin as modified above in claim 12 discloses the nanocrystalline graphene comprises hydrogen of about 1 at% to about 20 at% [¶ [0067] of Shin).
Regarding claim 16, Sato in view of Shin as modified above in claim 12 discloses the nanocrystalline graphene has a density of about 1.6 g/cc to about 2.1 g/cc [¶ [0067] of Shin).
Regarding claim 17, Sato in view of Shin as modified above in claim 12 discloses surface of crystals of the nanocrystalline graphene is substantially perpendicular to a direction of stacking of the plurality of first graphene layers (Fig 7 of Sato in combination with Shin).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm.
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/RATISHA MEHTA/ Primary Examiner, Art Unit 2817
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