Prosecution Insights
Last updated: May 29, 2026
Application No. 18/521,994

INTERCONNECT STRUCTURE AND ELECTRONIC DEVICE INCLUDING THE SAME

Non-Final OA §102§103
Filed
Nov 28, 2023
Priority
Nov 29, 2022 — RE 10-2022-0163251
Examiner
MEHTA, RATISHA
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
90%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
96%
With Interview

Examiner Intelligence

Grants 90% — above average
90%
Career Allowance Rate
565 granted / 631 resolved
+21.5% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Fast prosecutor
1y 12m
Avg Prosecution
18 currently pending
Career history
654
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
68.7%
+28.7% vs TC avg
§102
11.5%
-28.5% vs TC avg
§112
4.1%
-35.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 631 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-6 and 18-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Barth (US 2014/0291819; hereinafter Barth). Regarding claim 1, Fig 9 of Barth discloses an interconnect structure comprising: a first dielectric layer (634; Fig 9; ¶ [0073]) including a trench (630; Fig 9; ¶ [0062]); a first conductive layer (218/220/222; Fig 9; ¶ [0039]) in the trench (630; Fig 9; ¶ [0062]), the first conductive layer (218/220/222; Fig 9; ¶ [0039]) including a plurality of first graphene layers (222; Fig 9; ¶ [0039]) stacked in a direction from an inner surface of the trench toward a center of the trench (Fig 9); a second dielectric layer (632; Fig 9; ¶ [0069]) on the first dielectric layer (634; Fig 9; ¶ [0073]), the second dielectric layer (632; Fig 9; ¶ [0069]) including a through hole (650/640; Fig 9; ¶ [0073]) extending to the trench (630; Fig 9; ¶ [0062]); and a second conductive layer (218/220/222; Fig 9; ¶ [0039]) in the through hole (650/640; Fig 9; ¶ [0073]). Regarding claim 2, Fig 9 of Barth discloses the second conductive layer (218/220/222; Fig 9; ¶ [0039]) comprises a plurality of second graphene layers (222; Fig 9; ¶ [0039]). Regarding claim 3, Fig 9 of Barth discloses the second conductive layer (218/220/222; Fig 9; ¶ [0039]) comprises a metal material (¶ [0042]). Regarding claim 4, Fig 9 of Barth discloses the first conductive layer (218/220/222; Fig 9; ¶ [0039]) further comprises a metal layer (218; Fig 9; ¶ [0039]) contacting the inner surface (Fig 9) of the trench (630; Fig 9; ¶ [0062]). Regarding claim 5, Fig 9 of Barth discloses the second conductive layer (218/220/222; Fig 9; ¶ [0039]) a plurality of second graphene layers (222; Fig 9; ¶ [0039]). Regarding claim 6, Fig 9 of Barth discloses the second conductive layer (218/220/222; Fig 9; ¶ [0039]) comprises a metal material (¶ [0042]). Regarding claim 18, Fig 9 of Barth discloses an electronic device comprising:a substrate (216; Fig 9; ¶ [0039]) and an interconnect structure (900; Fig 9; ¶ [0088]) on the substrate, wherein the interconnect structure includes a first dielectric layer (634; Fig 9; ¶ [0073]) including a trench (630; Fig 9; ¶ [0062]), a first conductive layer (218/220/222; Fig 9; ¶ [0039]) in the trench (630; Fig 9; ¶ [0062]), a second dielectric layer (632; Fig 9; ¶ [0069]) on the first dielectric layer (634; Fig 9; ¶ [0073]), and a second conductive layer (218/220/222; Fig 9; ¶ [0039]), wherein the first conductive layer (218/220/222; Fig 9; ¶ [0039]) includes a plurality of first graphene layers (222; Fig 9; ¶ [0039]) stacked in a direction from an inner surface of the trench toward a center of the trench (Fig 9) the second dielectric layer (632; Fig 9; ¶ [0069]) including a through hole (650/640; Fig 9; ¶ [0073]) extending to the trench (630; Fig 9; ¶ [0062]) and the second conductive layer (218/220/222; Fig 9; ¶ [0039]) is in the through hole (650/640; Fig 9; ¶ [0073]). Regarding claim 19, Fig 9 of Barth discloses the second conductive layer (218/220/222; Fig 9; ¶ [0039]) comprises a plurality of second graphene layers (222; Fig 9; ¶ [0039]). Regarding claim 20, Fig 9 of Barth discloses the interconnect structure further comprises a third dielectric layer (634 (middle one); Fig 9; ¶ [0073]) on the second dielectric layer (632; Fig 9; ¶ [0069]), wherein the second dielectric layer (632; Fig 9; ¶ [0069]) and the third dielectric layer (634 (middle one); Fig 9; ¶ [0073]) define the through hole (650/640; Fig 9; ¶ [0073]) such that through hole (650/640; Fig 9; ¶ [0073]) extends through the second dielectric layer to the third dielectric layer and penetrates (Fig 9) through the third dielectric layer, and the second conductive layer (218/220/222; Fig 9; ¶ [0039]) fills the through hole (650/640; Fig 9; ¶ [0073]). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 7-10 are rejected under 35 U.S.C. 103 as being unpatentable over Barth (US 2014/0291819; hereinafter Barth) in view of Yu et al (US 2022/0384374; hereinafter Yu). Regarding claim 7, Fig 9 of Barth discloses the first dielectric layer (634; Fig 9; ¶ [0073]) comprises a low-k dielectric material (¶ [0072]). However Barth does not expressly disclose the first dielectric layer comprises a dielectric material having a dielectric constant of 3.6 or less. In the same field of endeavor, Yu discloses the dielectric constants of the low-k dielectric materials is lower than 3.0 (¶ [0018]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the first dielectric layer comprises a dielectric material having a dielectric constant of 3.6 or less for the purpose of using well known and suitable materials known in the art for forming the layer comprising low-k dielectric material. Regarding claim 8, Fig 9 of Barth discloses the second dielectric layer comprises a dielectric material (632; Fig 9; ¶ [0069]) comprises a dielectric material that is selectively depositable on the first dielectric layer (634; Fig 9; ¶ [0073]). Regarding claim 9, Fig 9 of Barth discloses a third dielectric layer (634 (middle one); Fig 9; ¶ [0073]) on the second dielectric layer (632; Fig 9; ¶ [0069]), wherein the second dielectric layer (632; Fig 9; ¶ [0069]) and the third dielectric layer (634 (middle one); Fig 9; ¶ [0073]) define the through hole (650/640; Fig 9; ¶ [0073]) such that through hole (650/640; Fig 9; ¶ [0073]) extends through the second dielectric layer to the third dielectric layer and penetrates (Fig 9) through the third dielectric layer, and the second conductive layer (218/220/222; Fig 9; ¶ [0039]) fills the through hole (650/640; Fig 9; ¶ [0073]). Regarding claim 10, Fig 9 of Barth discloses the third dielectric layer (634; Fig 9; ¶ [0073]) comprises a low-k dielectric material (¶ [0072]). However Barth does not expressly disclose the third dielectric layer comprises a dielectric material having a dielectric constant of 3.6 or less. In the same field of endeavor, Yu discloses the dielectric constants of the low-k dielectric materials is lower than 3.0 (¶ [0018]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the third dielectric layer comprises a dielectric material having a dielectric constant of 3.6 or less for the purpose of using well known and suitable materials known in the art for forming the layer comprising low-k dielectric material. Claim(s) 11 is rejected under 35 U.S.C. 103 as being unpatentable over Barth (US 2014/0291819; hereinafter Barth) in view of Kuo et al (US 2019/0006230; hereinafter Kuo). Regarding claim 11, Barth does not expressly disclose a width of the trench is equal to or less than 10 nm. In the same field of endeavor, Fig 1B of Kuo discloses a width of a trench (107; Fig 1B) is equal to 5 nm (¶ [0029]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that a width of a trench in the interconnects is with in the claimed range in order to control the aspect ratio of the trench (¶ [0029]). Claim(s) 12-17 are rejected under 35 U.S.C. 103 as being unpatentable over Barth (US 2014/0291819; hereinafter Barth) in view of Shin et al (US 2021/0355582; hereinafter Shin). Regarding claim 12, Barth does not expressly disclose the plurality of first graphene layers comprise intrinsic graphene or nanocrystalline graphene. In the same field of endeavor, Shin discloses graphene layers can comprise nanocrystalline graphene (¶ [0062]). Accordingly it would have been obvious to the person in the ordinary skill in the art before the effective filing date of the invention such that the graphene layers comprises nanocrystalline graphene in order to form the graphene layer having a nano-level grain size which is less than those of the general crystalline graphene (¶ [0067]). Regarding claim 13, Barth in view of Shin as modified above in claim 12 discloses the nanocrystalline graphene (¶ [0062] of Shin) comprises crystals having a size of about 0.5 nm to about 200 nm (¶ [0067] of Shin). Regarding claim 14, Barth in view of Shin as modified above in claim 12 discloses in the nanocrystalline graphene a ratio of carbons having an sp2 bond structure to total carbons is about 50% to about 99% (¶ [0067] of Shin). Regarding claim 15, Barth in view of Shin as modified above in claim 12 discloses the nanocrystalline graphene comprises hydrogen of about 1 at% to about 20 at% (¶ [0067] of Shin). Regarding claim 16, Barth in view of Shin as modified above in claim 12 discloses the nanocrystalline graphene has a density of about 1.6 g/cc to about 2.1 g/cc (¶ [0067] of Shin). Regarding claim 17, Barth in view of Shin as modified above in claim 12 discloses surface of crystals of the nanocrystalline graphene is substantially perpendicular to a direction of stacking of the plurality of first graphene layers (Fig 9 of Barth in combination with Shin). Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: Chin et al (US 2023/0154792; Chin discloses forming a conductive interconnect structure with barriers and liners of varying thicknesses) Bao et al (US 2013/0113102; Bao discloses forming a semiconductor interconnect structure having a graphene-based barrier metal layer) Any inquiry concerning this communication or earlier communications from the examiner should be directed to RATISHA MEHTA whose telephone number is (571)270-7473. The examiner can normally be reached Monday-Friday: 9:00am - 5:00 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eliseo Ramos Feliciano can be reached at 571-272-7925. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /RATISHA MEHTA/Primary Examiner, Art Unit 2817
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Prosecution Timeline

Nov 28, 2023
Application Filed
Feb 11, 2026
Non-Final Rejection mailed — §102, §103
Apr 28, 2026
Interview Requested
May 05, 2026
Applicant Interview (Telephonic)
May 11, 2026
Response Filed
May 15, 2026
Examiner Interview Summary

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Prosecution Projections

1-2
Expected OA Rounds
90%
Grant Probability
96%
With Interview (+6.4%)
1y 12m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 631 resolved cases by this examiner. Grant probability derived from career allowance rate.

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