DETAILED ACTION
This office action is in response to the application filed on November 28, 2023. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgement
The present office action is made with all the suggested amendments being fully considered. Accordingly, claims 1-8 are currently pending in this application.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 11/28/2023 and 1/27/2026 are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, 7 are rejected under 35 U.S.C. 103 as being unpatentable over Chien (US 2019/0386132) in view of Nishiguchi (US 2014/0284773) in further view of Shimomura (US 2019/0088776).
With respect to Claim 1, Chien shows (Fig. 1-4) most aspects of the current invention including a method for manufacturing a semiconductor device comprising:
(a) preparing a semiconductor substrate (100) of a first conductive type (N), the semiconductor substrate having an upper surface and a lower surface
(b) after the step of (a), forming a trench (102) in the semiconductor substrate at the upper surface of the semiconductor substrate
(c) after the step of (b), forming a first insulating film (104) inside the trench and on the upper surface of the semiconductor substrate
(d) after the step of (c), forming a field plate electrode (106’) on the first insulating film located inside the trench (Fig 3)
(e) after the step of (d), thinning the first insulating film (thickness T1 turns into thickness T2’ par 31), and exposing an upper portion (106’S) of the field plate electrode from the first insulating film (Fig 4)
(f) after the step of (e), performing an etching process to the upper portion of the field plate electrode exposed from the first insulating film (Fig 5-6)
Furthermore, although Chien discloses performing an etching process to the upper portion of the field plate electrode exposed from the first insulating film (Fig 5-6) and after the step of (f), removing the first insulating film located on the upper surface of the semiconductor substrate (See Fig 8), Chien fails to show performing an isotropic etching process to the upper portion of the field plate electrode and also fails to show recessing the first insulating film located inside the trench such that an upper surface of the first insulating film located inside the trench is positioned lower than the upper portion of the field plate electrode in cross-sectional view; and (h) after the step of (g), in cross-sectional view, forming a gate insulating film inside the trench positioned over the upper surface of the first insulating film, and forming a second insulating film on an upper surface of the upper portion of the field plate electrode and on a side surface of the field plate electrode exposed from the first insulating film in the step of (g).
On the other hand, and in the same field of endeavor, Nishiguchi teaches (Fig. 1-8B) a method for manufacturing a semiconductor device comprising forming a field plate electrode (30) on a first insulating film (17) located inside a trench (15) of a semiconductor substrate (10), removing the first insulating film located on the upper surface of the semiconductor substrate (Fig 4A-4B) and recessing the first insulating film located inside the trench such that an upper surface of the first insulating film located inside the trench is positioned lower than an upper portion of the field plate electrode in cross-sectional view (Fig 5A) and after that step, performing a step of forming a gate insulating film (21) inside the trench positioned over the upper surface of the first insulating film, and forming a second insulating film (23) on an upper surface of the upper portion of the field plate electrode and on a side surface of the field plate electrode exposed from the first insulating film (Fig 5B). Nishiguchi teaches the field plate electrode enhances a dielectric breakdown strength between the source and the electrode by controlling an electric field in the drift layer which is positioned in the -Z direction with respect to the gate electrodes (par 23) and by enhancing the dielectric strength, the ON resistance of the semiconductor device can be lowered (par 57).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein after the step of (f), recessing the first insulating film located inside the trench such that an upper surface of the first insulating film located inside the trench is positioned lower than the upper portion of the field plate electrode in cross-sectional view; and (h) after the step of (g), in cross-sectional view, forming a gate insulating film inside the trench positioned over the upper surface of the first insulating film, and forming a second insulating film on an upper surface of the upper portion of the field plate electrode and on a side surface of the field plate electrode exposed from the first insulating film in the step of (g) in the device of Chien, as taught by Nishiguchi because the field plate electrode enhances a dielectric breakdown strength between the source and the electrode by controlling an electric field in the drift layer which is positioned in the -Z direction with respect to the gate electrodes and by enhancing the dielectric strength, the ON resistance of the semiconductor device can be lowered.
Furthermore, Nishiguchi depicts a method step of performing an isotropic etching process to the upper portion of the field plate electrode (30) may be performed in the method for manufacturing to provide the field plate electrode having a different shape. However, Nishiguchi does not teach that particular method step.
On the other hand, and in the same field of endeavor, Shimomura 2019 teaches (Fig. 5A-7B) a method for manufacturing a semiconductor device comprising forming a field plate electrode (20) on a first insulating film (18) located inside a trench (50) of a semiconductor substrate (12), and etching may be performed by chemical dry etching (CDE) or wet etching to etch back the field plate electrode (20) (par 52).
Accordingly, one of ordinary skill in the semiconductor manufacturing art would have known that field plate electrodes may be etched using an isotropic etching process. Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have a method step of performing an isotropic etching process to the upper portion of the field plate electrode, in the method of Chien in view of Nishiguchi, because such isotropic etching process is known in the semiconductor manufacturing art for etching field plate electrodes, as suggested by Shimomura 2019, and applying a known method step for its conventional purpose would have been a common sense choice by one skilled in the semiconductor art. KSR Int’l Co. v. Teleflex Inc., 550 U.S, 82 USPQ2d 1385 (2007).
With respect to Claim 2, Shimomura 2019 teaches (Fig. 5A-7B) wherein the field plate electrode is made of a polycrystalline silicon film, and wherein the isotropic etching process in the step of (f) is a chemical dry etching process using CF4 gas.
With respect to Claim 3, Shimomura 2019 teaches (Fig. 5A-7B) wherein a corner of the upper portion of the field plate electrode is chamfered or rounded by the chemical dry etching process (See Fig 1A; the field plate electrode is rounded, See Fig 7A; the field plate electrode is chamfered)
With respect to Claim 4, Nishiguchi teaches (Fig. 1-8B) wherein the first insulating film is made of a silicon oxide film, and wherein each of the step of (e) and the step of (g) is performed with a wet etching process using a solution containing hydrofluoric acid (par 35).
With respect to Claim 7, Nishiguchi teaches (Fig. 1-8B) wherein the step of (d) includes steps of: (dl) forming a first conductive film (47) on the first insulating film to fill inside of the trench (Fig. 6A); (d2) after the step of (dl), forming the first conductive film (50) remaining inside the trench as the field plate electrode by removing the first conductive film located outside the trench (Fig. 6B); and (d3) after the step of (d2), selectively recessing the field plate electrode such that a part of the field plate electrode remains as a contact portion (Fig 7A).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Chien (US 2019/0386132) in view of Nishiguchi (US 2014/0284773) and in further view of Shimomura (US 2019/0088776) and Shin (US 2022/0302303).
With respect to Claim 5, Chien in view of Nishiguchi and in further view of Shimomura 2019 shows most aspects of the current invention. Furthermore, Nishiguchi teaches (Fig. 1-8B) wherein in the step of (h), the gate insulating film and the second insulating film are formed by a thermal oxidization process using oxygen gas (par 39). However, the combination of references do not teach a thermal oxidization process using oxygen gas under a condition that is equal to or higher than 1000°C, and that is equal to or lower than 1200°C.
On the other hand, and in the same field of endeavor, Shimomura teaches (Fig. 5A-7B) a method for manufacturing a semiconductor device comprising forming a field plate electrode (400) on a first insulating film (210-230) located inside a trench (200) of a semiconductor substrate (105), forming a gate insulating film (320) inside the trench positioned over the upper surface of the first insulating film, and forming a second insulating film (250) on an upper surface of the upper portion of the field plate electrode, wherein the gate insulating film and the second insulating film are formed by a thermal oxidization process using oxygen gas under a condition at a high temperature of 800° C. or higher.
Regarding claim 5, the courts have held that differences in the temperature will not support the patentability of subject matter encompassed by the prior art unless there is evidence indicating such temperatures are critical. “Where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the workable ranges by routine experimentation.” See In re Aller, 220 F.2d 454, 456, 105, USPQ 233, 235 (CCPA 1955).
Since the applicant has not established the criticality of the temperatures and similar temperatures are known in the art (see e.g. Kobayashi), it would have been obvious to one of the ordinary skill in the art to use these values in the device of Chien in view of Nishiguchi and in further view of Shimomura 2019.
Criticality: The specification contains no disclosure of either the critical nature of the claimed temperatures or any unexpected results arising therefrom. Where patentability is said to be based upon particular chosen dimensions or upon another variable recited in a claim, the applicant must show that the chosen dimensions are critical. In re Woodruff, 919 F.2d 1575, 1578, 16 USPQ 2d 1934, 1936 (Fed Cir. 1990).
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Chien (US 2019/0386132) in view of Nishiguchi (US 2014/0284773) and in further view of Shimomura (US 2019/0088776) and Shimomura (US 2014/0284709).
With respect to Claim 6, Chien in view of Nishiguchi and in further view of Shimomura 2019 shows most aspects of the current invention. Furthermore, Shimomura 2019 teaches (Fig. 5A-7B) a method for manufacturing a semiconductor device comprising forming a gate insulating film (320) inside the trench positioned over the upper surface of the first insulating film, and forming a second insulating film (250) on an upper surface of the upper portion of the field plate electrode, wherein the gate insulating film and the second insulating film are formed by a thermal oxidization process using oxygen gas under a condition at a high temperature of 800° C. or higher.
However, the combination of references do not teach wherein the step of (h) includes steps of: (hi) forming a first silicon oxide film inside the trench positioned over the first insulating film and on the upper surface of the field plate electrode and also the side surface of the field plate electrode which are exposed from the first insulating film by a thermal oxidization process using oxygen gas under a condition that is equal to or higher than 1000°C, and that is equal to or lower than 12000°C and (h2) forming a second silicon oxide film on the first silicon oxide film by a CVD method, and wherein each of the gate insulating film and the second insulating film includes the first silicon oxide film and the second silicon oxide film.
On the other hand, and in the same field of endeavor, Shimomura 2014 teaches (Fig. 5A-8B) a method for manufacturing a semiconductor device comprising forming a field plate electrode (DIF1) on a first insulating film (SINS1) located inside a trench (200) of a semiconductor substrate (SUB), forming a gate insulating film (GINS) inside the trench positioned over the upper surface of the first insulating film, and forming a second insulating film (SINS2) on an upper surface of the upper portion of the field plate electrode, and wherein the step of forming the gate insulating film and the second insulating film comprises forming a first silicon oxide film (DINS) inside the trench positioned over the first insulating film and on the upper surface of the field plate electrode and also the side surface of the field plate electrode which are exposed from the first insulating film by a thermal oxidization process, forming a second silicon oxide (DEPI) film on the first silicon oxide film by a CVD method and wherein each of the gate insulating film and the second insulating film includes the first silicon oxide film and the second silicon oxide film. Shimomura 2014 teaches this arrangement allows the device to suppress the occurrence of the leakage and the decrease in withstanding voltage (par 63).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein the step of (h) includes steps of: (hi) forming a first silicon oxide film inside the trench positioned over the first insulating film and on the upper surface of the field plate electrode and also the side surface of the field plate electrode which are exposed from the first insulating film by a thermal oxidization process using oxygen gas under a condition that is equal to or higher than 1000°C, and that is equal to or lower than 12000°C and (h2) forming a second silicon oxide film on the first silicon oxide film by a CVD method, and wherein each of the gate insulating film and the second insulating film includes the first silicon oxide film and the second silicon oxide film in the device of Chien in view of Nishiguchi and in further view of Shimomura 2019, as taught by Shimomura 2014 to provide a device that will suppress the occurrence of the leakage and the decrease in withstanding voltage.
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Chien (US 2019/0386132) in view of Nishiguchi (US 2014/0284773) and in further view of Shimomura (US 2019/0088776) and Oasa (US 2022/0085208).
With respect to Claim 8, Chien in view of Nishiguchi and in further view of Shimomura 2019 shows most aspects of the current invention. Furthermore, Nishiguchi teaches (Fig. 1-8B) further comprising steps of: (i) after the step of (h), inside the trench, forming a gate electrode (50) on the field plate electrode recessed by the step of (d3) via the second insulating film (Fig 6B); (j) after the step of (i), on the upper surface of the semiconductor substrate, forming a body region (20) inside the semiconductor substrate so as to be formed shallower than the trench, a conductive type of the body region being a second conductive type opposite the first conductive type (Fig 7A); (k) after the step of (j), forming a source region (25) inside the body region, a conductive type of the source region being the first conductive type (Fig. 7B); (l) after the step of (k), forming an interlayer insulating film (33) on the upper surface of the semiconductor substrate so as to cover the trench (Fig 7B).
However, the combination of references do not teach (m) after the step of (l), forming a first hole penetrating through each of the interlayer insulating film and the source region, and reaching an inside of the body region; (n) after the step of (l), forming a second hole penetrating through the interlayer insulating film, and reaching the gate electrode; (o) after the step of (l), forming a third hole penetrating through the interlayer insulating film, and reaching the contact portion; (p) after the step of (m), the step of (n) and the step of (o), forming each of a source electrode and a gate wiring on the interlayer insulating film; and (q) after the step of (p), forming a drain electrode on the lower surface of the semiconductor substrate, wherein the gate wiring is electrically connected to the gate electrode via the second hole, wherein the source electrode is electrically connected to each of the source region and the body region via the first hole, and is electrically connected to the field plate electrode via the third hole, and wherein the drain electrode is electrically connected to the semiconductor substrate.
On the other hand, and in the same field of endeavor, Oasa teaches (Fig. 3-12B, 18-19) a method for manufacturing a semiconductor device comprising forming a field plate electrode (20) on a first insulating film (41) located inside a trench (T) of a semiconductor substrate (12), further comprising steps of inside the trench, forming a gate electrode (30) on the field plate electrode, forming a body region (13) inside the semiconductor substrate so as to be formed shallower than the trench, forming a source region (14) inside the body region, forming an interlayer insulating film (46) on the upper surface of the semiconductor substrate so as to cover the trench and further comprising forming a first hole (Fig. 18; hole on left portion of the device comprising plug 62; par 76) penetrating through each of the interlayer insulating film and the source region, and reaching an inside of the body region; forming a second hole (Fig. 19; hole penetrating the insulating film 46 comprising plug 71; par 75) penetrating through the interlayer insulating film, and reaching the gate electrode, forming a third hole (Fig. 18; hole in the center portion of the device comprising plug 62; par 74) penetrating through the interlayer insulating film, and reaching the contact portion, forming each of a source electrode (52) and a gate wiring (70) on the interlayer insulating film (par 74-75); and forming a drain electrode (51) on the lower surface of the semiconductor substrate, wherein the gate wiring is electrically connected to the gate electrode via the second hole, wherein the source electrode is electrically connected to each of the source region and the body region via the first hole, and is electrically connected to the field plate electrode via the third hole, and wherein the drain electrode is electrically connected to the semiconductor substrate. Oasa teaches doing so to design a device in which a gate electrode that is located in a trench controls a channel that conducts a current in the vertical direction of a semiconductor layer by performing the device design after improving the trade-off between the on-resistance and the parasitic capacitance that occurs due to the positional relationship between the gate electrode and the base region (par 3) and further to suppress the fluctuation of the on-resistance and capacitance that may occur in the actual device due to fluctuation when manufacturing (par 3 and 71).
Therefore, it would have been obvious to one of ordinary skill in the art, and before the effective filing date of the claimed invention to have wherein (m) after the step of (l), forming a first hole penetrating through each of the interlayer insulating film and the source region, and reaching an inside of the body region; (n) after the step of (l), forming a second hole penetrating through the interlayer insulating film, and reaching the gate electrode; (o) after the step of (l), forming a third hole penetrating through the interlayer insulating film, and reaching the contact portion; (p) after the step of (m), the step of (n) and the step of (o), forming each of a source electrode and a gate wiring on the interlayer insulating film; and (q) after the step of (p), forming a drain electrode on the lower surface of the semiconductor substrate, wherein the gate wiring is electrically connected to the gate electrode via the second hole, wherein the source electrode is electrically connected to each of the source region and the body region via the first hole, and is electrically connected to the field plate electrode via the third hole, and wherein the drain electrode is electrically connected to the semiconductor substrate in the device of Chien in view of Nishiguchi and in further view of Shimomura 2019, as taught by Oasa to design a device in which a gate electrode that is located in a trench controls a channel that conducts a current in the vertical direction of a semiconductor layer by performing the device design after improving the trade-off between the on-resistance and the parasitic capacitance that occurs due to the positional relationship between the gate electrode and the base region and further to suppress the fluctuation of the on-resistance and capacitance that may occur in the actual device due to fluctuation when manufacturing.
Conclusion
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/Q.A.B/ Examiner, Art Unit 2814
/WAEL M FAHMY/ Supervisory Patent Examiner, Art Unit 2814