DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the entirety of quenching element of claim 17 must be shown in conjunction with the other elements of claim 17 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 1-5, 7-10, 13,16-19 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
a. As to claim 1 17 and 18 Applicant does not have support for an insulating region configured to electrically isolate a plurality of semiconductor elements from each other and the like
This implies that there are already existing devices that are isolated at the time of forming the isolation. This is not supported by the disclosure; devices are formed after the isolation is formed. The claim should recite an insulating region configured to electrically isolate a plurality of semiconductor elements to be formed
b. As to claim 1 applicant does not have full support for a second substrate including the second semiconductor element and the second wiring layer other than the second substrate comprising the entire thinned semiconductor the method as claimed would include methods where only the device and wiring is transferred to a separate substrate and then bonded. Applicant teaches the second substrate is the thinned semiconductor layer and wiring.
c. As to claims 17 18 for substantially the same reason applicant does not have support for
joining a first substrate including the first semiconductor element and the first wiring layer and a second substrate including the second semiconductor element and the second wiring layer so as to be electrically connected to each other
Applicant does not teach transferring only the wiring and the element to a substrate than bonding the semiconductor layer and the wiring layer are the substrates.
Further applicant does not have support for transferring the first element to a new substrate and then having this first substrate bonded to a second the substrates are first and second semiconductor layers and the corresponding wirings
d. As to claim 3, Applicant does not have support after forming a through-hole configured to penetrate through the insulating region, performing heat treatment on the second substrate and forming a thermal oxide film on a side surface of the insulating region. The thermal treatment is performed at the time of forming the isolation
Paragraph 113:
A difference from Fig. 8 is that a thermal oxide film 711 is formed on the side surfaces of the insulation separation region before a semiconductor device formation process. As mentioned above, thermal oxidation treatment is performed at temperatures of 800 to 1100°C. This temperature range generally belongs to the highest temperature range of other heat treatment temperatures in the wafer fabrication process. Thus, in one embodiment, thermal oxidation is not performed after the process that is performed at a lower temperature and can be performed early in the wafer process before transistor formation. For example, the melting point of Al used in metal wiring is 660°C, and thermal oxidation cannot be performed after wiring processing. Note that this insulation isolation region and the thermal oxide films 711 may be formed by the shallow trench isolation (STI) method, which is a common process in the wafer fabrication process.
Paragraph 136:
Fig. 19 is a flow diagram illustrating a manufacturing method of the photoelectric conversion apparatus illustrated in Figs. 16 to 18. Fig. 19 corresponds to Figs. 11A and 11B of the first embodiment. Fig. 19 differs from Figs. 11A and 11B in that not SPADs but CMOS image sensors are formed on the first substrate 11. As mentioned above, thermal oxidation treatment is performed at temperatures of 800 to 1100°C. This temperature range generally belongs to the highest temperature range of other heat treatment temperatures in the wafer fabrication process. Thus, in one embodiment, thermal oxidation is not performed after the process that is performed at a lower temperature and can be performed early in the wafer process before transistor formation. For example, the melting point of Al used in metal wiring is 660°C, and thermal oxidation cannot be performed after wiring processing. Note that this insulation isolation region and the thermal oxide films 711 may be formed by the shallow trench isolation (STI) method, which is a common process in the wafer fabrication process.
There is no disclosure or any indication that the thermal treatment occurs after the through hole is formed.
Further how does one form a thermal oxide film on a side surface of the insulating region it is covered by the wiring layer and corresponding interlayer dielectric. It appears applicant is referring to the thermal oxide in the trenches it appears to be a liner that is form in figure 19 before the isolation see figure 19 the lined at the bottommost 21.
e. As to claim 17, recitation of forming a second semiconductor element including a quenching element and a second wiring layer on the side where the third plane is provided is not supported. Paragraph 107 indicates:
Fig. 9 is an example of an enlarged cross-sectional view of the second substrate taken along IX-IX illustrated in Figs. 6A and 6B. Fig. 9 illustrates a cross-section of the MOS transistor (a first element) of the quenching device section 411, a MOS transistor (a second element) of the second circuit section 413, the insulation isolation region 422, and the through-via 421. A first gate oxide film 451 having a first thickness is arranged as the gate oxide film in the MOS transistor of the quenching device section 411, and a second gate oxide film 452 having a second thickness is arranged as the gate oxide film in the MOS transistor of the second circuit section 413. In general, the thicker the gate oxide film, the higher the breakdown voltage of the transistor. Thus, transistors with different breakdown voltages may be arranged in the second substrate 21.
Thus, the quenching device is not a single element since 411 is a first transistor of the quenching device. Since it is a plurality of semiconductor devices the quenching device cannot be formed until the wiring is formed to interconnect the devices. Thus, applicant does not have support for forming a second semiconductor element including a quenching element and a second wiring layer on the side where the third plane is provided.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, 7-10, 13, 16-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As to claim 1 17 18, applicant does not link a second semiconductor element to the plurality of semiconductor elements
Claim 16 clarifies this but makes no sense since the isolation at the time of formation must isolate the element but the second element does not exist at the point forming the isolation
As to claims 1 17 and 18 recitation of so as to be electrically connected is unclear what is being electrically connected it appears to mean so as to electrically connect the first element to the second element
As to claim 1, Claim 1 recites:
forming a first semiconductor element and a first wiring layer on a side of the first semiconductor laver - there is no first semiconductor layer recited.
forming, from a side of the second semiconductor layer where the third plane is provided, an insulating region configured to electrically isolate a plurality of semiconductor elements from each other- applicant has not established any devices on the second semiconductor layer or has interconnected the first substrate and the second layer thus it is unclear how the insulating region isolates elements that do not exist.
and joining a first substrate including the first semiconductor element and the first wiring layer it is unclear if the first substrate is the same or different than the already existing substrate.
so as to be electrically connected to each other, wherein the through-electrode is connected to a bonding portion provided at a bonding interface between the first substrate and the second substrate Applicant has not established the through electrode is part of the second substrate only the second semiconductor element and wiring are part of the second substrate.
As to claim 5, applicant does not link the bonding portion to the bonding interface already recited in claim 1.
As to claim 17, recitation of quenching element is unclear and confusing
Applicant is reciting a function of the element the specification merely set forth it may contain a transistor (paragraph 107) but gives no description of quenching circuit.
Thus, applicant is setting forth a function without define the corresponding structure see mpep 2173.05g. In this instance it is unclear what is included an excluded as “quenching element.”
As to claim 17, recitation of from a side of the second semiconductor layer where the third plane is provided, an insulating region configured to electrically isolate a plurality of semiconductor elements from each other there are no semiconductor elements recited at this point, so it is unclear how the isolation accomplishes the outcome.
As to claim 18, recitation of forming, from a side of the second semiconductor layer where the third plane is provided, an insulating region configured to electrically isolate a plurality of semiconductor elements from each other since there are now elements claimed at this point. Further applicant fails to link the elements to the second semiconductor element.
Further wherein the through-electrode is electrically connected to the quenching element applicant has not established the through electrode is part of the second substrate.
As to claim 18, recitation wherein the through-electrode is connected to one of a cathode terminal and an anode terminal of the avalanche photodiode is unclear when it occurs.
It appears applicant means joining a first substrate including the first semiconductor element and the first wiring layer and a second substrate including the second semiconductor element and the second wiring layer so as to be electrically connected to each other such that the through-electrode is connected to one of a cathode terminal and an anode terminal of the avalanche photodiode.
As to claim 19, recitation of wherein the one of the cathode terminal and the anode terminal is electrically connected to the second wiring layer through the through-electrode since it is unclear when this occurs in the process.
The claims are confusing since they require semiconductor elements to be formed before the isolation but then form the elements after forming the isolation.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 5, and 16 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Kim 20230403866.
a. As to claim 1, Kim teaches A semiconductor device manufacturing method comprising: preparing a first semiconductor layer (figures 1-2 and 7a item 101 paragraph 27) having a first plane and a second plane facing the first plane (top and bottom); preparing a second semiconductor layer having a third plane and a fourth plane facing the third plane (see also figure 7e item 201 top and bottom); forming a first semiconductor element (items 150) and a first wiring layer (items 198-180) on a side of the first semiconductor laver where the first plane is provided (see figure 7a); forming an insulating region from a side of the second semiconductor layer where the third plane is provided (item 210b figure 7e), an insulating region configured to electrically isolate a plurality of semiconductor elements (item 210b), to be formed, from each other )figure 7e-7f item 210 b); after the forming the insulating region, forming the semiconductor elements including a second semiconductor element (figure 7f items 220) and a second wiring layer on the side where the third plane is provided (item 280); after the forming the second semiconductor element and the second wiring layer, thinning the second semiconductor layer (figure 7g ) from a side where the fourth plane is provided to expose the insulating region; after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region and be connected to the second wiring layer (figure 7h paragraph 118); and joining a first substrate comprising the first wiring and first semiconductor layer and a second substrate including the second semiconductor layer and the second wiring layer so as to be electrically connected the elements to each other, wherein the through-electrode is connected to a bonding portion provided at a bonding interface between the first substrate and the second substrate (applicant does not state it must be directly connected it can be connected through other wiring as such the vias further figure 11 shows a stack of such devices thus the next level would include another first semiconductor layer figure 7a or 7e and 254 is directly bonded to this device at a bonding interface thus whether it is a direct bonding connection or indirect connection Kim reasonably teaches both).
b. As to claim 5, Kim teaches wherein in the joining, a wiring line whose main component is copper and that is included in the first wiring layer (item 198 paragraph 45) and a wiring line whose main component is copper (item 298 paragraph 45) and that is included in the second wiring layer are bonded together (figure 7I), and an insulation member included in the first wiring layer and an insulation member included in the second wiring layer are bonded together (figure 74 The first and second substrate structures S1 and S2 may be bonded by hybrid bonding including copper (Cu)-to-copper (Cu) bonding and dielectric-dielectric bonding).
c. As to claim 16, Kim teaches the devices to be isolated are include the second semiconductor element.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 and 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Bachman (8742535).
a. As to claim 2, Kim teaches wherein in the forming the through-electrode, a through-hole configured to penetrate through the insulating region is formed from the side where the fourth plane is provided (figure 7h item 260 based on the disclosure and the figure the via must be formed through the 4th plane). Kim teaches forming with a conductive material (paragraph 118)
Kim does not explicitly, and the through-hole is filled with metal.
Bachman teaches filling the through hole with a metal (figures 4-7 item 710 fills the trench) Bachman teaches non-limiting examples of the types of electrically conductive material 710 that could be used includes copper, tungsten, gold, polysilicon, conductive polymers.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the conductive via as copper to use known materials for known and expected outcomes of good electrically conductive vias for electrical communication.
c. As to claim 4, Kim teaches further comprising: forming an interlayer film on the side of the second substrate where the fourth plane is provided (290C); and forming a wiring line whose main component on the interlayer in a plane parallel to the fourth plane of the second substrate (item 254).
Kim does not teach copper being the main component.
However, Kim paragraph 45 teach the use of copper Backman also teaches teach using for interconnects non-limiting examples of the types of electrically conductive material 710 that could be used includes copper, tungsten, gold, polysilicon, conductive polymers, or similar materials familiar to those skilled in the art. In some embodiments, to fill a deep opening 610 (e.g., in some embodiments where the substrate thickness 615 (FIG. 6) is about 50 microns or greater) it can be advantageous for the filling step 165 to include sputter depositing or other processes for forming a metal seed layer (e.g., copper) on the interior side walls 615 of the second-side TSV opening 610 (including on any intervening insulating layers 312, 314 on the opening's sidewalls 316) and then electrodepositing or otherwise forming a bulk metal layer (e.g., copper) to fill the remainder of the opening 610. Other methods to fill the opening 610 in accordance with step 165 include spin-on processes or other processes familiar to one of ordinary skill in the art. One skilled in the art would also be familiar with further steps such as CMP to remove excess electrically conductive material 710 from the second side 215 surface 306, such that the material 710 is only present in the opening 610.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form wiring 254 from primarily of copper to ensure good electrical connection and low resistances in the device.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Fukuzumi (20160079164).
a. As to claims 7-8 Kim does not teach:
further comprising: after the joining, forming, from the side where the second plane is provided, an opening through which a wiring line included in the first wiring layer is exposed to outside the semiconductor device
further comprising: after the joining, forming, from the side where the second plane is provided, an opening through which a wiring line included in the second wiring layer is exposed to outside the semiconductor device.
Fukuzumi teaches after the joining (figure 6), forming, from the side where the second plane is provided (back side of the nand), an opening through which a wiring line included in the first wiring layer is exposed to outside the semiconductor device (figure 7 item 97 exposes wiring corresponding to the first wiring).
Fukuzumi also teaches after the joining (figure 6), forming, from the side where the second plane is provided (backside of the nand), an opening through which a wiring line included in the second wiring layer is exposed to outside the semiconductor device (item 121 which when formed would expose 122 which corresponds to the second wiring).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to after the joining, forming, from the side where the second plane is provided, an opening through which a wiring line included in the first wiring layer is exposed to outside the semiconductor device
And or
after the joining, forming, from the side where the second plane is provided, an opening through which a wiring line included in the second wiring layer is exposed to outside the semiconductor device.
To provide the desired access connection to the device providing allowing the desired integration.
Claim(s) 10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Liu (20200328176).
a. As to claims 10 and 13 Kim teaches wherein the side of the first substrate where the first plane is provided and the side of the second substrate where the third plane is provided are bonded together (figure 7I)
Kim does not teach further comprising: preparing a third substrate having a fifth plane and a sixth plane facing the fifth plane; forming a third semiconductor device and a third wiring layer on a side of the third substrate where the fifth plane is provided; and joining the second substrate and the third substrate so as to be electrically connected to each other.
Liu teaches preparing a third substrate (figure 12a item 1002) having a fifth plane and a sixth plane facing the fifth plane (top and bottom); forming a third semiconductor device (1008) and a third wiring layer (1014 and 1016) on a side of the third substrate where the fifth plane is provided (figure 12a); and joining the second substrate and the third substrate so as to be electrically connected to each other (figure 12B).
Liu further teaches wherein the side of the first substrate where the first plane is provided and the side of the second substrate where the third plane is provided are bonded together, and the side of the second substrate where the fourth plane is provided and the side of the third substrate where the fifth plane is provided are bonded together (figure 12b).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to have bonded the device in the manner Liu to provide the desired access and orientation providing lower resistance path for the desired memory functions.
Claim Rejections - 35 USC § 103
Claim(s) 1,9, 17, 18, and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (202300439255) in view of Kim and Hung (20210375959)
a. As to claims 1, 9, 17, and 18 Yang teaches, A semiconductor device manufacturing method comprising: preparing a first substrate (figure 3 item 102) having a first plane and a second plane facing the first plane (top and bottom); preparing a second substrate (item 202) having a third plane and a fourth plane facing the third plane (top and bottom; forming a first semiconductor device (item 103 and 117 )and a first wiring layer on a side of the first substrate where the first plane is provided (item 108); , forming a second semiconductor device (item 203) and a second wiring layer on the side where the third plane is provided (item 208) , forming a second semiconductor device and a second wiring layer on the side where the third plane is provided (items 212 ); forming a through electrode through the second substrate connected to the second wiring layer (item 212 connect to 208). Yang teaches photodetectors (paragraph 17 item 117). Yang teaches a quenching element connected to the photodiode (a transistor). Applicant gives no disclosure of what is and is not a quenching element beyond a transistor in paragraph 107, thus it is substantially the same as described and meets the claim limitation. Yang further teaches wherein the through-electrode is connected to one of a cathode terminal and an anode terminal of the avalanche photodiode. Recitation of connected is no indicative of a direct connection and allows for intervening elements the device forms an integrated circuit, so all the elements are connected including the transistors to the anodes and cathodes of the photodiodes and in the same manner the TSV are electrically connected to the transistor (quenching elements) and the anodes and cathodes of the photodiodes.
Yang does not teach forming an insulating region from a side of the second substrate where the third plane is provided; after the forming the insulating region, forming a second semiconductor device and a second wiring layer on the side where the third plane is provided; after the forming the second semiconductor device and the second wiring layer, thinning the second substrate from a side where the fourth plane is provided to expose the insulating region; after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region.
Kim teaches A semiconductor device manufacturing method comprising: preparing a first semiconductor layer (figures 1-2 and 7a item 101 paragraph 27) having a first plane and a second plane facing the first plane (top and bottom); preparing a second semiconductor layer having a third plane and a fourth plane facing the third plane (see also figure 7e item 201 top and bottom); forming a first semiconductor element (items 150) and a first wiring layer (items 198-180) on a side of the first semiconductor laver where the first plane is provided (see figure 7a); forming an insulating region from a side of the second semiconductor layer where the third plane is provided (item 210b figure 7e), an insulating region configured to electrically isolate a plurality of semiconductor elements (item 210b), to be formed, from each other )figure 7e-7f item 210 b); after the forming the insulating region, forming the semiconductor elements including a second semiconductor element (figure 7f items 220) and a second wiring layer on the side where the third plane is provided (item 280); after the forming the second semiconductor element and the second wiring layer, thinning the second semiconductor layer (figure 7g ) from a side where the fourth plane is provided to expose the insulating region; after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region and be connected to the second wiring layer (figure 7h paragraph 118); and joining a first substrate comprising the first wiring and first semiconductor layer and a second substrate including the second semiconductor layer and the second wiring layer so as to be electrically connected the elements to each other, wherein the through-electrode is connected to a bonding portion provided at a bonding interface between the first substrate and the second substrate (applicant does not state it must be directly connected it can be connected through other wiring as such the vias further figure 11 shows a stack of such devices thus the next level would include another first semiconductor layer figure 7a or 7e and 254 is directly bonded to this device at a bonding interface thus whether it is a direct bonding connection or indirect connection Kim reasonably teaches both).
Thus it would have been obvious to one of ordinary skill in the art at the time of filing form the through vias using the method of Kim by forming an insulating region from a side of the second substrate where the third plane is provided; after the forming the insulating region, forming a second semiconductor device and a second wiring layer on the side where the third plane is provided ; after the forming the second semiconductor device and the second wiring layer, thinning the second substrate from a side where the fourth plane is provided to expose the insulating region; after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region and be connected to the second wiring layer; and joining the first substrate and the second substrate so as to be electrically connected to each other.
In order to use known technique to provide expected outcomes of providing through vias for interconnection with wirings.
Yang does not teach wherein the first semiconductor device includes an avalanche photodiode.
Hung teaches providing photodiodes as avalanche photodiodes (paragraph 70 and 102).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the photodiodes as avalanche photodiodes for improved sensitivity and high speeds.
b. As to claim 19, recitation of electrically connected is broad and does not imply direct connection Thus Yang’s integrated circuit provides wherein the one of the cathode terminal and the anode terminal is electrically connected to the second wiring layer through the through-electrode.
Response to Arguments
Applicant's arguments filed 8/24/2026 have been fully considered but they are not persuasive.
Applicant argues:
However, KIM does not disclose the configuration described in the presently amended claims. In particular, the Examiner alleges that that the second element isolation layer 210B and the via 260 correspond to the "insulating region" and the "through-electrode" of pending Claim 1, respectively. The via 260 in KIM is a part of a third wiring structure described in paragraphs [0065] to [0068] and connects an upper circuit interconnection line 252 provided on the upper side of the substrate 201 and a first lower circuit interconnection line 282 provided on the lower side of the substrate 201. On the other hand, a second bonding metal layer 298 located at the bonding interface is a part of a separate second bonding structure described in paragraphs [0071] and [0072] and is connected to a second lower circuit interconnection line 284 though a second bonding via 295.
According to paragraphs [0065] and [0070], the third wiring structure including the via 260 can be used to supply a power supply voltage or a ground voltage to the circuit device 220, while the second wiring structure can be used for connection with the first substrate structure Si, and thus they are explained as structures transmitting different types of electrical signals. Therefore, KIM does not clearly and directly disclose the specific relationship of "wherein the through-electrode is connected to a bonding portion provided at a bonding interface between the first substrate and the second substrate" as presently amended Claim 1.
As such, KIM does not disclose at least "preparing a first substrate having a first plane and a second plane facing the first plane; preparing a second semiconductor layer having a third plane and a fourth plane facing the third plane; forming a first semiconductor element and a first wiring layer on a side of the first semiconductor layer where the first plane is provided; forming, from a side of the second semiconductor layer where the third plane is provided, an insulating region configured to electrically isolate a plurality of semiconductor elements from each other; after forming the insulating region, forming a second semiconductor element and a second wiring layer on the side where the third plane is provided; after forming the second semiconductor element and the second wiring layer, thinning the second semiconductor layer from a side where the fourth plane is provided to expose the insulating region; after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region and be connected to the second wiring layer; and joining a first substrate including the first semiconductor element and the first wiring layer and a second substrate including the second semiconductor element and the second wiring layer so as to be electrically connected to each other, wherein the through-electrode is connected to a bonding portion provided at a bonding interface between the first substrate and the second substrate" as presently claimed.
At issue, electrically connected does not mean directly connected. All of the elements of the devices themselves are connected to bonding interfaces thus the via is electrically connected to the bonded interface via these devices. Further figure 11 shows stacking multiple of such devices a 250 is directly connected to s1 of the chip above it.
Thus, Kim teaches the limitations, and applicant should clarify the intent of electrically connected.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
Prosecution Insights