DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of group I species C in the reply filed on 3/10/2026 is acknowledged.
Claims 6 ,11-12, 14 and 15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected devices and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 3/10/2026.
Claim 6 requires wherein the first plane of the first substrate and the fourth plane of the second substrate are bonded together so as to face each other.
Claim 13 requires wherein the side of the first substrate where the first plane is provided and the side of the second substrate where the third plane is provided are bonded together.
Thus claim 6 should go with species A.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 3 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. Claim 1 requires forming an insulating region from a side of the second substrate where the third plane is provided after the forming the insulating region, forming a second semiconductor device and a second wiring layer on the side where the third plane is provided;
The isolation as described in the specification is 422 the isolation appears to include the trench see figure 12 and figure 8 item 21. The cross hashed line cannot be the insulating region since to have it formed on the semiconductor devices 202.
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Claim 3 then requires further comprising: before the forming the insulating region, performing heat treatment on the second substrate and forming a thermal oxide film on a side surface of the insulating region. What applicant appears to be referring to is the formation to is the formation item 711 figure 11a paragraph 113:
A difference from Fig. 8 is that a thermal oxide film 711 is formed on the side surfaces of the insulation separation region before a semiconductor device formation process. As mentioned above, thermal oxidation treatment is performed at temperatures of 800 to 1100°C. This temperature range generally belongs to the highest temperature range of other heat treatment temperatures in the wafer fabrication process. Thus, in one embodiment, thermal oxidation is not performed after the process that is performed at a lower temperature and can be performed early in the wafer process before transistor formation. For example, the melting point of Al used in metal wiring is 660°C, and thermal oxidation cannot be performed after wiring processing. Note that this insulation isolation region and the thermal oxide films 711 may be formed by the shallow trench isolation (STI) method, which is a common process in the wafer fabrication process.
Since the insulating region must include the insulating includes the trench 711 that applicant does not have support for: before the forming the insulating region, performing heat treatment on the second substrate and forming a thermal oxide film on a side surface of the insulating region since the specification seems to imply it is either after forming the trench or during the insulating region formation not wholly before.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-5, and 7-10 and 13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
a. As to claim 1, it is unclear what steps are required for: forming an insulating region from a side of the second substrate where the third plane is provided.
There are no specific steps in the specification of what constitutes form the insulating region further the figures are unclear.
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There is no discussion of forming a separate insulation step of forming an insulation layer in the trench and then forming the semiconductor devices. In fact, it appears the insulating layer portion in the trench is formed as the same material as what covers the semiconductor devices. The specification gives no guidance as to what steps other steps are required. Based on figure 8 it appears the trench formation is insulating region.
b. As to claim 4 recites and forming a wiring line whose main component is copper and exposed on the fourth plane of the second substrate. The wiring is in/on the interlayer (see figure 11a 333 formed in or on item 402) Thus the plane is not the 4th plane of the substrate but a plane parallel to the 4th since the 4th plane is at the substrate.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 5 is/are rejected under 35 U.S.C. 102a2 as being anticipated by Kim 20230403866.
a. As to claim 1, Kim teaches A semiconductor device manufacturing method comprising: preparing a first substrate (figure 7d item101) having a first plane (top of item 101) and a second plane facing the first plane (bottom of item 101); preparing a second substrate (figure 7e item 201) having a third plane and a fourth plane facing the third plane (top and bottom respectively); forming a first semiconductor device items 102-155 figure 7C0 and a first wiring layer on a side of the first substrate where the first plane is provided (item 170 180 and or item 190); forming an insulating region from a side of the second substrate where the third plane is provided (210a and 2010 b are formed in figure 7e); after the forming the insulating region, forming a second semiconductor device and a second wiring layer on the side where the third plane is provided (figure 7f items 220 and wiring item 280 and 290); after the forming the second semiconductor device and the second wiring layer, thinning the second substrate from a side where the fourth plane is provided to expose the insulating region (figure 7G); after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region and be connected to the second wiring layer (figure 7H item 260); and joining the first substrate and the second substrate so as to be electrically connected to each other (figure 7I).
b. As to claim 5, Kim teaches wherein in the joining, a wiring line whose main component is copper and that is included in the first wiring layer (item 198 paragraph 45) and a wiring line whose main component is copper (item 298 paragraph 45) and that is included in the second wiring layer are bonded together (figure 7I), and an insulation member included in the first wiring layer and an insulation member included in the second wiring layer are bonded together (figure 74 The first and second substrate structures S1 and S2 may be bonded by hybrid bonding including copper (Cu)-to-copper (Cu) bonding and dielectric-dielectric bonding).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2-4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Bachman (8742535).
a. As to claim 2, Kim teaches wherein in the forming the through-electrode, a through-hole configured to penetrate through the insulating region is formed from the side where the fourth plane is provided (figure 7h item 260 based on the disclosure and the figure the via must be formed through the 4th plane) . Kim teaches forming with a conductive material (paragraph 118)
Kim does not explicitly and the through-hole is filled with metal.
Bachman teaches filling the through hole with a metal (figures 4-7 item 710 fills the trench) Bachman teaches Non-limiting examples of the types of electrically conductive material 710 that could be used includes copper, tungsten, gold, polysilicon, conductive polymers.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the conductive via as copper to use known materials for known and expected outcomes of good electrically conductive vias for electrical communication.
b. As to claim 3 Kim does not teach during the forming the insulating region, performing heat treatment on the second substrate and forming a thermal oxide film on a side surface of the insulating region.
Bachman teach providing a passivation (item 314 figure 3B to figure 4) during the formation of the insulating region.
Further forming thermal oxide using anneal/heat treatments was known to passivate the surface of semiconductor and remove dangling bonds.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to include a thermal oxidation of the sidewalls of the trenches via a heat treatment to remove dangling bonds on the surface of the trench to ensure good deposition of insulating films deposited to form the insulating regions and remove undesired charges from the surface of the trench.
c. As to claim 4, Kim teaches further comprising: forming an interlayer film on the side of the second substrate where the fourth plane is provided (290C); and forming a wiring line whose main component on the interlayer in a plane parallel to the fourth plane of the second substrate (item 254).
Kim does not teach copper being the main component.
However, Kim paragraph 45 teach the use of copper Backman also teaches teach using for interconnects Non-limiting examples of the types of electrically conductive material 710 that could be used includes copper, tungsten, gold, polysilicon, conductive polymers, or similar materials familiar to those skilled in the art. In some embodiments, to fill a deep opening 610 (e.g., in some embodiments where the substrate thickness 615 (FIG. 6) is about 50 microns or greater) it can be advantageous for the filling step 165 to include sputter depositing or other processes for forming a metal seed layer (e.g., copper) on the interior side walls 615 of the second-side TSV opening 610 (including on any intervening insulating layers 312, 314 on the opening's sidewalls 316) and then electrodepositing or otherwise forming a bulk metal layer (e.g., copper) to fill the remainder of the opening 610. Other methods to fill the opening 610 in accordance with step 165 include spin-on processes or other processes familiar to one of ordinary skill in the art. One skilled in the art would also be familiar with further steps such as CMP to remove excess electrically conductive material 710 from the second side 215 surface 306, such that the material 710 is only present in the opening 610.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form wiring 254 from primarily of copper to ensure good electrical connection and low resistances in the device.
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Fukuzumi (20160079164).
a. As to claims 7-8 Kim does not teach:
further comprising: after the joining, forming, from the side where the second plane is provided, an opening through which a wiring line included in the first wiring layer is exposed to outside the semiconductor device
further comprising: after the joining, forming, from the side where the second plane is provided, an opening through which a wiring line included in the second wiring layer is exposed to outside the semiconductor device.
Fukuzumi teaches after the joining (figure 6) , forming, from the side where the second plane is provided (back side of the nand), an opening through which a wiring line included in the first wiring layer is exposed to outside the semiconductor device (figure 7 item 97 exposes wiring corresponding to the first wiring).
Fukuzumi also teaches after the joining (figure 6), forming, from the side where the second plane is provided (backside of the nand), an opening through which a wiring line included in the second wiring layer is exposed to outside the semiconductor device (item 121 which when formed would expose 122 which corresponds to the second wiring).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to after the joining, forming, from the side where the second plane is provided, an opening through which a wiring line included in the first wiring layer is exposed to outside the semiconductor device
And or
after the joining, forming, from the side where the second plane is provided, an opening through which a wiring line included in the second wiring layer is exposed to outside the semiconductor device.
To provide the desired access connection to the device providing allowing the desired integration.
Claim(s) 10 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kim in view of Liu (20200328176).
a. As to claims 10 and 13 Kim teaches wherein the side of the first substrate where the first plane is provided and the side of the second substrate where the third plane is provided are bonded together (figure 7I)
Kim does not teach further comprising: preparing a third substrate having a fifth plane and a sixth plane facing the fifth plane; forming a third semiconductor device and a third wiring layer on a side of the third substrate where the fifth plane is provided; and joining the second substrate and the third substrate so as to be electrically connected to each other.
Liu teaches preparing a third substrate (figure 12a item 1002) having a fifth plane and a sixth plane facing the fifth plane (top and bottom); forming a third semiconductor device (1008) and a third wiring layer (1014 and 1016) on a side of the third substrate where the fifth plane is provided (figure 12a); and joining the second substrate and the third substrate so as to be electrically connected to each other (figure 12B).
Liu further teaches wherein the side of the first substrate where the first plane is provided and the side of the second substrate where the third plane is provided are bonded together, and the side of the second substrate where the fourth plane is provided and the side of the third substrate where the fifth plane is provided are bonded together (figure 12b).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to have bonded the device in the manner Liu to provide the desired access and orientation providing lower resistance path for the desired memory functions.
Claim Rejections - 35 USC § 103
Claim(s) 1 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang (202300439255) in view of Kim and Hung (20210375959)
a. As to claim 1 and 9 Yang teaches, A semiconductor device manufacturing method comprising: preparing a first substrate (figure 3 item 102) having a first plane and a second plane facing the first plane (top and bottom); preparing a second substrate (item 202) having a third plane and a fourth plane facing the third plane (top and bottom; forming a first semiconductor device (item 103 and 117 )and a first wiring layer on a side of the first substrate where the first plane is provided (item 108); , forming a second semiconductor device (item 203) and a second wiring layer on the side where the third plane is provided (item 208) , forming a second semiconductor device and a second wiring layer on the side where the third plane is provided (items 212 ); forming a through electrode through the second substrate connected to the second wiring layer (item 212 connect to 208). Yang teaches photodetectors (paragraph 17 item 117)
Yang does not teach forming an insulating region from a side of the second substrate where the third plane is provided; after the forming the insulating region, forming a second semiconductor device and a second wiring layer on the side where the third plane is provided; after the forming the second semiconductor device and the second wiring layer, thinning the second substrate from a side where the fourth plane is provided to expose the insulating region; after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region.
Kim teaches forming an insulating region from a side of the second substrate where the third plane is provided (210a and 2010b are formed in figure 7e); after the forming the insulating region, forming a second semiconductor device and a second wiring layer on the side where the third plane is provided (figure 7f items 220 and wiring item 280 and 290); after the forming the second semiconductor device and the second wiring layer, thinning the second substrate from a side where the fourth plane is provided to expose the insulating region (figure 7G); after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region and be connected to the second wiring layer (figure 7H item 260); and joining the first substrate and the second substrate so as to be electrically connected to each other (figure 7I).
Thus it would have been obvious to one of ordinary skill in the art at the time of filing form the through vias using the method of Kim by forming an insulating region from a side of the second substrate where the third plane is provided; after the forming the insulating region, forming a second semiconductor device and a second wiring layer on the side where the third plane is provided ; after the forming the second semiconductor device and the second wiring layer, thinning the second substrate from a side where the fourth plane is provided to expose the insulating region; after exposing the insulating region, forming a through-electrode configured to penetrate through the insulating region and be connected to the second wiring layer; and joining the first substrate and the second substrate so as to be electrically connected to each other.
In order to use known technique to provide expected outcomes of providing through vias for interconnection with wirings.
Yang does not teach wherein the first semiconductor device includes an avalanche photodiode.
Hung teaches providing photodiodes as avalanche photodiodes (paragraph 70 and 102).
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form the photodiodes as avalanche photodiodes for improved sensitivity and high speeds.
Conclusion
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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