DETAILED ACTION
This Office Action is in response to an application that was filed on 11/28/2023. Claims 1-19 are presented for examination consideration.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 2, 3, 7, 11, and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Semmelmeyer et al. (US20170018816A1 and Semmelmeyer hereinafter).
Regarding claim 1, Semmelmeyer discloses a semiconductor module (item 70 of Fig. 3 and ¶[0034] shows and indicates semiconductor module 70 {3DIC [three-dimensional integrated circuits structure] 70}) comprising: a module substrate that has a plurality of substrate side pads on a surface (items 60, 22 of Fig. 3 and ¶[0021-0022_0025_0028 & 0034-0035] shows and indicates module substrate 60 {fifth die 60} that has the plurality of substrate side pads 22_60 {first connectors 22 that connected to fifth die 60} on a surface); a first member that is mounted on a mounting surface of the module substrate, and includes a semiconductor substrate including a compound semiconductor and a first electronic circuit on the semiconductor substrate (items 62, 34, 38 of Fig. 3 and ¶[0021-0022_0025_0028 & 0034-0035] shows and indicates first member 62 {interposer 62} that is mounted on the mounting surface of module substrate 60; where first member 62 includes semiconductor substrate 62-substate {substrate of interposer 62} including compound semiconductor 34 {TSVs 34 [through silicon vias]} and first electronic circuit 38 {first side interconnect components 38} on semiconductor substrate 62-substate); a second member that is bonded to an upper surface of the first member, and includes a semiconductor layer configured of a single semiconductor thinner than the semiconductor substrate and a second electronic circuit on the semiconductor layer (items 54, 36, 22, 54, 32 of Fig. 3 and ¶[0021-0022_0025-0026_0028 & 0034-0035] shows and indicates second member 54 {second die 54} that is bonded {bonding that occurs between interposer 62 and second die 54 through the bonding of first connectors 22} to the upper surface of first member 62; where second member 54 includes semiconductor layer 36-between-22-within-54 {layer between interconnects 36 within second die 54 and the surface of the first connectors 22 that are connecting between interposer 62 and second die 54} configured of a single semiconductor thinner than semiconductor substrate 62-substate; and where second electronic circuit 32_54 {TSVs 32 within second die 54} is on semiconductor layer 36-between-22-within-54); a first pad that is on the first member and is connected to the first electronic circuit (item 40 of Fig. 3 and ¶[0025 & 0028] shows and indicates first pad 40 {second side interconnect components 40} that is on first member 62 and is connected to first electronic circuit 38 {through TSV 34}); a second pad that is on the second member and is connected to the second electronic circuit (items 22, 54, 52, 28 of Fig. 3 and ¶[0021-0022_0025_0028 & 0034-0035] shows and indicates second pad 22_54_52 {pad formed by first connectors 22 bonding/connecting second die 54 and first die 52} that is on second member 54 and is connected to second electronic circuit 32_54 {through fourth connector 28}); a first wire that connects the first pad and one of the plurality of substrate side pads to each other (item 66 of Fig. 3 and ¶[0035] shows and indicates first wire 66 {bond wire 66} that connects first pad 40 and one of the plurality of substrate side pads 22_60 to each other); a second wire that connects the second pad and one of the plurality of substrate side pads to each other (item 68 of Fig. 3 and ¶[0035] shows and indicates second wire 68 {bond wire 68} that connects second pad 22_54_52 and one of the plurality of substrate side pads 22_60 to each other); and an inter-member connection wire including a conductor film that is on the first member and the second member and connects the first electronic circuit and the second electronic circuit to each other (items 38, 36, 62, 54 of Fig. 3 and ¶[0021-0022_0025-0026_0028 & 0034-0035] shows and indicates inter-member connection wire 38_36_54 {interconnection between first side interconnect components 38 and interconnects 36 within second die 54} including conductor film 62_38_54_36 {first side interconnect components 38 embedded within interposer 62 connecting to interconnects 36 embedded within second die 54} that is on first member 62 and second member 54 and connects first electronic circuit 38 and second electronic circuit 32_54 to each other).
Regarding claim 2, Semmelmeyer discloses a semiconductor module, wherein in plan view, the second member is smaller than the first member, and the first pad is at a position that does not overlap the second member, and the first pad is at a position lower than the second pad with the mounting surface of the module substrate as a height reference (Fig. 3 and ¶[0021-0022_0025_0028 & 0034-0035] shows where in plan view, second member 54 is smaller than first member 62; and where first pad 40 is at a position that does not overlap second member 54; and where first pad 40 is at the position lower than second pad 22_54_52 with the mounting surface of module substrate 60 as the height reference).
Regarding claim 3, Semmelmeyer discloses a semiconductor module, wherein the second electronic circuit is on a surface of the semiconductor layer that faces the first member, and the semiconductor module further includes a via conductor that extends in a thickness direction from a surface opposite to the surface on which the second electronic circuit is present and connects the second pad and the second electronic circuit to each other (item 36, 54 of Fig. 3 and ¶[0021-0022_0026 & 0034-0035] shows and indicates where second electronic circuit 32_54 is on the surface of semiconductor layer 36-between-22-within-54 that faces first member 62; and where and semiconductor module 70 further includes via conductor 36-portion-54 {portion of interconnects 36 that is embedded in second die 54} that extends in the thickness direction from a surface opposite to the surface on which second electronic circuit 32_54 is present and connects second pad 22_54_52 and second electronic circuit 32_54 to each other).
Regarding claim 7, Semmelmeyer discloses a semiconductor module, wherein an end portion of the first wire connected to the first pad is higher than an end portion connected to the substrate side pad with respect to a normal direction of the mounting surface of the module substrate (item 36, 54 of Fig. 3 and ¶[0025_0028 & 0035] shows where the end portion of first wire 66 that is connected to first pad 40 is higher than the end portion that is connected to substrate side pads 22_60 with respect to the normal direction of the mounting surface of module substrate 60).
Regarding claim 11, see the rejection of claim 3 above.
Regarding claim 15, see the rejection of claim 7 above.
Claim 19 is rejected under 35 U.S.C. 102(a)(1) as being anticipated by Semmelmeyer.
Regarding claim 19, Semmelmeyer discloses a semiconductor device (item 70 of Fig. 3 and ¶[0034] shows and indicates semiconductor device 70 {3DIC [three-dimensional integrated circuits structure] 70}) comprising: a first member that includes a semiconductor substrate including a compound semiconductor, and a first electronic circuit on an upper surface which is one surface of the semiconductor substrate (items 62, 34, 38 of Fig. 3 and ¶[0021-0022_0025_0028 & 0034-0035] shows and indicates first member 62 {interposer 62} that includes semiconductor substrate 62-substate {substrate of interposer 62} including compound semiconductor 34 {TSVs 34 [through silicon vias]}; where first member 62 includes first electronic circuit 38 {first side interconnect components 38} that is on the upper surface of one of the surface of semiconductor substrate 62-substate); a second member that is bonded to the upper surface of the first member, and includes a semiconductor layer configured of a single semiconductor thinner than the semiconductor substrate and a second electronic circuit on the semiconductor layer (items 54, 36, 22, 54, 32 of Fig. 3 and ¶[0021-0022_0025-0026_0028 & 0034-0035] shows and indicates second member 54 {second die 54} that is bonded {bonding that occurs between interposer 62 and second die 54 through the bonding of first connectors 22} to the upper surface of first member 62; where second member 54 includes semiconductor layer 36-between-22-within-54 {layer between interconnects 36 within second die 54 and the surface of the first connectors 22 that are connecting between interposer 62 and second die 54} configured of a single semiconductor thinner than semiconductor substrate 62-substate; and where second electronic circuit 32_54 {TSVs 32 within second die 54} is on semiconductor layer 36-between-22-within-54); a first pad that is on the first member and is connected to the first electronic circuit (item 40 of Fig. 3 and ¶[0025 & 0028] shows and indicates first pad 40 {second side interconnect components 40} that is on first member 62 and is connected to first electronic circuit 38 {through TSV 34}); a second pad that is on the second member and is connected to the second electronic circuit (items 22, 54, 52, 28 of Fig. 3 and ¶[0021-0022_0025_0028 & 0034-0035] shows and indicates second pad 22_54_52 {pad formed by first connectors 22 bonding/connecting second die 54 and first die 52} that is on second member 54 and is connected to second electronic circuit 32_54 {through fourth connector 28}); and an inter-member connection wire configured of a conductor film that is on the first member and the second member and connects the first electronic circuit and the second electronic circuit to each other (items 38, 36, 62, 54 of Fig. 3 and ¶[0021-0022_0025-0026_0028 & 0034-0035] shows and indicates inter-member connection wire 38_36_54 {interconnection between first side interconnect components 38 and interconnects 36 within second die 54} configured of conductor film 62_38_54_36 {first side interconnect components 38 embedded within interposer 62 connecting to interconnects 36 embedded within second die 54} that is on first member 62 and second member 54 and connects first electronic circuit 38 and second electronic circuit 32_54 to each other).
Allowable Subject Matter
Entire Claims 4-6, 8-10, 12-14, and 16-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the primary reason for allowance is due to a semiconductor module, further comprising: a first common insulating film that continuously covers a region from an upper surface of the second member to the upper surface of the first member; and a cross wire configured of a conductor film connected to the first pad, wherein the cross wire is connected to the first pad at one end portion and is connected to the first electronic circuit at a position different from the first pad in a plan view.
Regarding claim 5, the primary reason for allowance is due to a semiconductor module, wherein at least one of the plurality of substrate side pads is for a ground, and the semiconductor module further includes a second common insulating film that is on the inter-member connection wire, a shield film configured of a conductor film that is on the second common insulating film and overlaps the inter-member connection wire in a plan view, and a third wire that connects the shield film and a ground pad among the plurality of substrate side pads to each other.
Regarding claim 6, the primary reason for allowance is due to a semiconductor module, wherein the second electronic circuit further includes a temperature dependent element whose characteristic changes according to a temperature, and a control circuit configured to control an operation of the first electronic circuit in accordance with the change in the characteristic of the temperature dependent element.
Regarding claim 8, the primary reason for allowance is due to a semiconductor module, wherein the second electronic circuit includes at least one switching transistor, the first electronic circuit includes a controlled circuit whose operating state is switched by on and off of the switching transistor, and the inter-member connection wire connects the switching transistor and the controlled circuit to each other dependent element.
Regarding claims 9-10, the primary reason for allowance is due to the dependency on claim 8.
Regarding claim 12, see the allowability subject matter of claim 4.
Regarding claim 13, see the allowability subject matter of claim 5.
Regarding claim 14, see the allowability subject matter of claim 6.
Regarding claim 16, see the allowability subject matter of claim 8.
Regarding claims 17-18, the primary reason for allowance is due to the dependency on claim 16.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUILLERMO J EGOAVIL whose telephone number is (571)270-1325. The examiner can normally be reached Mon-Fri 8:00-5:00.
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/GUILLERMO J EGOAVIL/Examiner, Art Unit 2847
/TIMOTHY J THOMPSON/Supervisory Patent Examiner, Art Unit 2847
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