DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to the claims filled on 11/28/2023 that has been entered, wherein claims 1-20 are pending.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/28/2023, 4/23/2024, 5/31/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “a second microelectronic device structure attached to the first microelectronic device structure and comprising a sub word line driver region vertically overlying and within a horizontal area of the staircase region, the sub word line driver region comprising sub word line drivers configured to provide a voltage to the first memory array region and the second memory array region by means of the conductive contact structures” must be shown or the features canceled from the claims. Similarly “a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising: sub word line drivers vertically above the sub-staircase structures and within horizontal boundaries of the staircase region, the sub word line drivers individually operably coupled to the first vertical stacks of memory cells and the second vertical stacks of memory cells by means of the conductive contact structures”. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation "the second horizontal direction" in line 21. There is insufficient antecedent basis for this limitation in the claim. Is the second horizontal direction the same or different than a second direction of line 18? For the purpose of examination, “the second horizontal direction” will be interpreted as “the second direction”.
Claims 10-16 depend on claim 9 and inherit it’s deficiencies.
Claim 16 presently recites the limitation “ the first memory array” in line 2. There is insufficient antecedent basis for this limitation in the claim. Is the first memory array the same or different than a first memory array region of claim 9, line 2? For the purpose of examination, “the first memory array” will be interpreted as “the first memory array region”.
Claim 16 presently recites the limitation “ the second memory array” in line 3. There is insufficient antecedent basis for this limitation in the claim. Is the second memory array the same or different than a second memory array region of claim 9, line 2? For the purpose of examination, “the second memory array” will be interpreted as “the second memory array region”.
Claim 17 presently recites the limitation “ first vertical stacks of access devices horizontally neighboring first vertical stacks of access devices” in line 8. How can the first vertical stacks of access devices horizontally neighbor itself? For the purpose of examination the limitation of “first vertical stacks of access devices horizontally neighboring first vertical stacks of access devices” will be interpreted as “first vertical stacks of access devices horizontally neighboring first vertical stacks of storage devices”.
Claim 17 presently recites the limitation “ second vertical stacks of access devices horizontally neighboring second vertical stacks of access devices” in line 11. How can the second vertical stacks of access devices horizontally neighbor itself? For the purpose of examination the limitation of “second vertical stacks of access devices horizontally neighboring second vertical stacks of access devices” will be interpreted as “second vertical stacks of access devices horizontally neighboring second vertical stacks of storage devices”.
Claims 18-20 depend on claim 17 and inherit it’s deficiencies.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0252386 A1) in view of Sharma et al. (US 2022/0375939 A1) .
Regarding claim 1, Lee teaches a microelectronic device(Fig. 2), comprising:
a first microelectronic device structure(SS2, SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051), comprising:
a first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051) comprising first vertical stacks of first memory cells(SS2, DS, ¶0041-44, ¶0051), each of the first cells(SS2, DS, ¶0041-44, ¶0051) comprising a storage device of a vertical stack of storage devices(DS, ¶0051) and a horizontally neighboring access device(SP, ¶0051) of a vertical stack of access devices(SP, ¶0051);
a second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051) comprising second vertical stacks of second cells(SS3, DS, ¶0041-44, ¶0051);
a staircase region(region of CL1) substantially horizontally centered in a first direction(D2) between the first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051) and the second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051), the staircase region(region of CL1) comprising:
a staircase structure(Fig. 3C) comprising:
a vertical stack of first conductive structures(portion of CL1 in CAR, ¶0048) horizontally extending through the staircase region(region of CL1) in the first direction(D2), the first conductive structures(portion of CL1 in CAR, ¶0048) in contact with the first cells(SS2, DS, ¶0041-44, ¶0051) and the second cells(SS3, DS, ¶0041-44, ¶0051); and
sub-staircase structures(portion of CL1 in CTR, ¶0048) individually comprising second conductive structures(portion of CL1 in CTR, ¶0048) horizontally extending from the vertical stack of first conductive structures(portion of CL1 in CAR, ¶0048) in a second direction(D1), vertically uppermost ones of the second conductive structures(portion of CL1 in CTR, ¶0048) of each sub-staircase structure defining steps of the sub-staircase structure(portion of CL1 in CTR, ¶0048),
horizontally neighboring ones of the sub-staircase structures(portion of CL1 in CTR, ¶0048) substantially evenly horizontally separated from one another in the first direction(D2).
Lee does not explicitly state first memory cells(SS2, DS, ¶0041-44, ¶0051) and the second cells(SS3, DS, ¶0041-44, ¶0051) are first dynamic random access memory (DRAM) cells and second DRAM cells. However Lee discloses that first memory cells(SS2, DS, ¶0041-44, ¶0051) and the second cells(SS3, DS, ¶0041-44, ¶0051) comprise a memory cell transistors including a capacitor(¶0037, ¶0041-44, ¶0051).
Sharma teaches a microelectronic device(Fig. 4) comprising first dynamic random access memory (DRAM) cells(400-1, ¶0079, ¶0076) and second DRAM cells(400-2, ¶0079, ¶0076). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Lee, to include first dynamic random access memory (DRAM) cells and second DRAM cells, as taught by Sharma, in order to address the limitation in density and standby power of some other types of memory devices(¶0017).
Regarding claim 5, Lee teaches the microelectronic device of claim 1, wherein each of the sub-staircase structures(portion of CL1 in CTR, ¶0048) defines a pair of the steps of the staircase structure(portion of CL1 in CTR, ¶0048).
Regarding claim 6, Lee teaches the microelectronic device of claim 1, wherein a vertical height of each of the sub-staircase structures(portion of CL1 in CTR, ¶0048) is different than a vertical height of each other of the sub-staircase structures(portion of CL1 in CTR, ¶0048).
Regarding claim 7, Lee teaches the microelectronic device of claim 1, wherein the first conductive structures(portion of CL1 in CAR, ¶0048) horizontally extend in substantially linear paths through the first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051), the second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051), and the staircase region(region of CL1).
Regarding claim 8, Lee teaches the microelectronic device of claim 1, wherein pairs of the first conductive structures(portion of CL1 in CAR, ¶0048) are vertically spaced from one another by an insulative structure(ILD2, ¶0064).
Claims 9-10, 12-13 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US 2019/0252386 A1).
Regarding claim 9, Lee teaches a memory device(Fig. 2), comprising:
a first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051) and a second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051), each of the first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051) and the second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051) comprising vertical stacks of memory cells(SS2, SS3, DS, ¶0041-44, ¶0051) comprising:
vertical stacks of access devices(SP, ¶0051);
vertical stacks of storage devices(DS, ¶0051) horizontally neighboring the vertical stacks of access devices(SP, ¶0051); and
a portion(portion of CL1 in CAR, ¶0048) of a vertical stack structure(CL1, ¶0048) comprising substantially linear first conductive structures(portion of CL1 in CAR, ¶0048) horizontally extending through the vertical stacks of memory cells(SS2, SS3, DS, ¶0041-44, ¶0051), the substantially linear first conductive structures(portion of CL1 in CAR, ¶0048) neighboring the memory cells(SS2, DS, ¶0041-44, ¶0051) of the vertical stack of memory cells(SS2, DS, ¶0041-44, ¶0051); and
a staircase region(region of CL1) horizontally between the first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051) and the second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051), the staircase region(region of CL1) comprising a staircase structure(Fig. 3C) comprising:
and
sub-staircase structures(portion of CL1 in CTR, ¶0048) horizontally extending from the vertical stack structure(CL1, ¶0048) in a second direction(D1) different than the first direction(D2),
the sub-staircase structures(portion of CL1 in CTR, ¶0048) individually comprising second conductive structures(portion of CL1 in CTR, ¶0048)(portion of CL1 in CTR, ¶0048) defining steps of the sub-staircase structures(portion of CL1 in CTR, ¶0048),
the steps of the sub-staircase structures(portion of CL1 in CTR, ¶0048) vertically descending in the second horizontal direction(D1).
Fig. 2 of Lee is not relied on to teach an additional portion of the vertical stack structure(CL1, ¶0048) horizontally extending in a first direction(D2) from the first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051), through the staircase region(region of CL1), and to the second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051).
Fig. 5 of Lee teaches a memory device comprising an additional portion(ML5, ¶0089) of the vertical stack structure(CL1, C1, C2 ML5, ¶0048, ¶0091-92) horizontally extending in a first direction(D2) from the first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051), through the staircase region(region of CL1), and to the second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the embodiment of Fig. 2 of Lee so that an additional portion of the vertical stack structure(CL1, ¶0048) horizontally extending in a first direction(D2) from the first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051), through the staircase region(region of CL1), and to the second memory array region(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051), as taught by the embodiment of Fig. 5 of Lee, in order to connect to a peripheral circuit region(¶0092).
Regarding claim 10, Lee teaches the memory device of claim 9, wherein the steps of the sub-staircase structures(portion of CL1 in CTR, ¶0048) vertically descend in the second direction(D1) away from [the portion of the] the vertical stack structure(CL1, ¶0048).
Regarding claim 12, Lee teaches the memory device of claim 9, wherein a quantity(length in D1 direction of portion of CL1 in CTR that is about one-half of the length of CL1 in CAR) of the sub-staircase structures(portion of CL1 in CTR, ¶0048) is about one-half a quantity of the first conductive structures(portion of CL1 in CAR, ¶0048).
Regarding claim 13, Lee teaches the memory device of claim 9, wherein each of the sub-staircase structures(portion of CL1 in CTR, ¶0048) comprises a different quantity(length in D1 direction) of the second conductive structures(portion of CL1 in CTR, ¶0048) than each other of the sub-staircase structures(portion of CL1 in CTR, ¶0048).
Regarding claim 16, Lee teaches the memory device of claim 9, wherein a horizontal distance from a center of the staircase structure to the first memory array region(SS2, DS, CL1, ¶0041-44, ¶0048, ¶0051) is about equal(Fig. 2) to a horizontal distance from the center of the staircase structure to the second memory array(SS3, DS, CL1, ¶0041-44, ¶0048, ¶0051).
Allowable Subject Matter
Claims 2-4 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 2, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “a second microelectronic device structure attached to the first microelectronic device structure and comprising a sub word line driver region vertically overlying and within a horizontal area of the staircase region, the sub word line driver region comprising sub word line drivers configured to provide a voltage to the first memory array region and the second memory array region by means of the conductive contact structures”.
Regarding dependent claim 3, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the first conductive structures comprise word lines configured to provide a voltage to the vertical stack of access devices of the first memory array region and the vertical stack of access devices of the second memory array region”.
Regarding dependent claim 4, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “a vertical height of the staircase structures decreases as the staircase structures extend away from the first memory array region in the first direction”.
Claims 11, 14-15 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding dependent claim 11, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “some of the steps of sub-staircase structures nearer to the first memory array region are vertically higher than some other of the steps of the sub-staircase structures nearer to the second memory array region”.
Regarding dependent claim 14, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “the second conductive structures horizontally extend in the second direction beyond horizontal boundaries of the vertical stack structure”.
Regarding dependent claim 15, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “an of claim 2 of each of the first memory array region and the second memory array region; and an additional staircase structure comprising: a portion of the additional vertical stack structure horizontally extending through the staircase region; and additional sub-staircase structures horizontally extending from the additional vertical stack structure”.
Claims 17-20 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
The following is a statement of reasons for the indication of allowable subject matter: Regarding dependent claim 17, the prior art of record neither anticipates nor renders obvious the claimed subject matter of the instant application as a whole either taken alone or in combination, in particular, prior art of record does not teach “a second microelectronic device structure attached to the first microelectronic device structure, the second microelectronic device structure comprising: sub word line drivers vertically above the sub-staircase structures and within horizontal boundaries of the staircase region, the sub word line drivers individually operably coupled to the first vertical stacks of memory cells and the second vertical stacks of memory cells by means of the conductive contact structures.”
Claims 18-20 depend on claim 17 and inherit its allowable subject matter.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Gomes et al. (US 20210/159229 A1) Discloses a memory device
Brewer et al. (US 2021/0375875 A1) Discloses a memory device
Tsai et al. (US 2023/0223343 A1) Discloses a memory device.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LAURA DYKES whose telephone number is (571)270-3161. The examiner can normally be reached M-F 9:30 am-5 pm.
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/LAURA M DYKES/Examiner, Art Unit 2892
Prosecution Insights