Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification The specification submitted 11/28/2023 has been accepted by the examiner . Drawings The drawings submitted on 11/28/2023 have been accepted by the examiner. Information Disclosure Statement s The information disclosure statement s (IDS) submitted recently have been considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1 , 5, and 8-9 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Ryu (US # 20160005803) . Regarding Claim 1 , Ryu teaches a thin film transistor array substrate (see Figs. 1-4 and corresponding text) , comprising: a substrate (101) including a display area (EA and DA ) and a non-display area ( not shown, but it would be an area surrounding the pixels ) around the display area; a plurality of pixels (P, a display has an array of pixels) in the display area; and a first thin film transistor ( STr ) disposed in each pixel, wherein the first thin film transistor includes: a first oxide semiconductor pattern (113; [0073] ) ; a first gate electrode (120a) overlapped with the first oxide semiconductor pattern (shown) ; a first lower conductive pattern (103) facing the first gate electrode with the first oxide semiconductor pattern interposed therebetween (shown) ; a first source electrode (133a) and a first drain electrode (136a) connected to the first oxide semiconductor pattern (shown) , respectively; and an electric field shielding pattern (left side of 106, especially see Figs. 3 and 4A) between the first oxide semiconductor pattern and the first lower conductive pattern (shown) . Regarding Claim 5 , Ryu teaches the thin film transistor array substrate of claim 2, wherein the electric field shielding pattern is disposed on the same layer as the second lower conductive pattern (both are shown on top of layer 104) . Regarding Claim 8 , Ryu teaches the thin film transistor array substrate of claim 1, wherein the first oxide semiconductor pattern (113) , the first lower conductive pattern (103) , and the electric field shielding pattern (106) are overlapped each other (see Fig. 3 showing vertical overlap) . Regarding Claim 9 , Ryu teaches the thin film transistor array substrate of claim 1, further comprising a light emitting device (E) connected to the driving thin film transistor, wherein light emitting device includes: an anode electrode (165) connected to the second drain electrode of the driving thin film transistor; a cathode electrode (173) corresponding to the anode electrode; and a light emitting layer (170) between the anode electrode and the cathode electrode. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim s 2-4 and 6-7 are rejected under 35 U.S.C. 103 a s being unpatentable over Ryu (US # 20160005803) in view of Wang (US # 20200083309 ). Regarding Claim 2 , Ryu teaches the thin film transistor array substrate of claim 1, further comprising a driving thin film transistor ( DTr ) in each pixel, w herein the driving thin film transistor includes: a second oxide semiconductor pattern (115; [0073] ) on the substrate; a second gate electrode (120b) overlapped with the second oxide semiconductor pattern (shown) ; a second source electrode (not shown ; see [0083] ) and a second drain electrode (136b) connected to the second oxide semiconductor pattern, respectively; and a second lower conductive pattern (right side of 106, see especially Figs. 3 or 4B) overlapped with the second oxide semiconductor pattern under the second oxide semiconductor pattern (shown) . Although Ryu discloses much of the claimed invention, it does not explicitly teach the TFT array substrat e wherein the second lower conductive pattern is connected to one of the second source electrode and the second drain electrode . Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Wang is in the same or analogous field, and it teaches a TFT array substrate (110) comprising a driving TFT ( first transistor M1) that is an oxide transistor ([110]), wherein a second lower conductive pattern (120) is connected to one of the second source electrode and the second drain electrode ( [00 18-19] teach electrical connection). A person having ordinary skill in the art would have recognized that modifying the driving transistor of Ryu with the lower conductive pattern suggested by Wang would be obvious. Specifically, the modification suggested by Wang would be to employ a TFT array substrate wherein the second lower conductive pattern is connected to one of the second source electrode and the second drain electrode . The ration ale for this obvious modification is that biased shields provide oxide-semiconductor sensitivity to light interference and E-fields ( [0068] ). This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of such shields are well known in the TFT art (see MPEP 2144.01). Regarding Claim 3 , Ryu teaches the thin film transistor array substrate of claim 2, wherein the first thin film transistor is a switching thin film transistor connected to a gate node of the driving thin film transistor (see Fig. 2 showing connection of STr to the D Tr gate) . Regarding Claim 4 , Ryu suggests the thin film transistor array substrate of claim 1, wherein the electric field shielding pattern is floated (shown in the embodiment of Fig. 4A) . Also, Wang teaches that floating or biasing the shielding patterns is an available set of options ([0087]). Such floating of an electrode provides benefits to V th and also to ESD and to parasitic capacitances. Regarding Claim 6 , Ryu suggests the comparative parasitic capacitances recited. Ryu teaches that the thickness and material (SiN vs. SiO) of these dielectric layers (layer 108 vs 116) are variable parameters used to tune the electrical characteristics of the devices. Through routine optimization of the material and thicknesses of layers 108/116, a PHOSITA would have arrived at the recited ratio of parasitic capacitances. A PHOSITA would be motivated to make buffer layer 108 thinner than gate insulation 116 so as to create a stronger electrical influence on the oxide semiconductor (to enhance the shielding effects). In regards to the gate dielectric above, the benefit is to reduce power consumption and RC delay in the gate of the TFT, which is something a designer must balance . Regarding Claim 7 , a lthough Ryu discloses much of the claimed invention, it does not explicitly teach the thin film transistor array substrate of claim 1, wherein the first lower conductive pattern is electrically connected to the first gate electrode . Nonetheless the prior art at the time the application was filed renders such non-explicit feature differences obvious, as explained below. For example, Wang is in the same or analogous field, and it teaches a thin film transistor (second transistor M2) wherein a first lower conductive pattern (130a) is electrically connected to a first gate electrode (32; [0022] The second shielding layer may be electrically connected to the gate electrode of the second TFT ) . A person having ordinary skill in the art would have recognized th at modifying the shield of Ryu with the shield biasing suggested by Wang would be obvious. Specifically, the modification suggested by Wang would be to employ a thin film transistor array substrate of claim 1, wherein the first lower conductive pattern is electrically connected to the first gate electrode . The rationale for this obvious modification is that biasing the shield with the M2 gate electrode provides synchronized shielding with the switching operation and it stabilizes V th against substrate noise. This would have been apparent to a person having ordinary skill in the art in reading both references because the existence and benefits of gate-biased shields are well known in the art (see MPEP 2144.01). Conclusion Citation of pertinent art: US 20190288048 A1 US 20210098549 A1 US 20140084286 A1 US 20210202634 A1 US 20200119119 A1 US 11594556 B2 Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT CHRISTOPHER A JOHNSON whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571) 272-9475 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT normally working Monday to Friday between 9 am and 6 pm Eastern Time . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CHRISTOPHER A JOHNSON/ Primary Examiner, Art Unit 2899