DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Information Disclosure Statement The information disclosure statement (IDS) submitted on February 24, 2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner. Claim Objections Claim 16 is objected to because of the following informalities: inconsistent terminologies. “ the third portions” and “the holes” should read “the two third portions” and “the plurality of holes”, respectively. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of the first paragraph of 35 U.S.C. 112(a): (a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention. The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112: The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention. Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. There is no support in the original specification (in the prior-filed application # 16/311,693 , filed on December 20 , 2018 ) for the claim limitations of “a source-drain contacting layer, disposed on the gate layer” , as recited in claim 1 (note: Fig. 2 shows that a horizontal portion of a source-drain contacting layer disposed over (not on) the gate layer) ; “ a projection of the fourth portion projected on the substrate is located within a projection of the one of the two third portions projected on the substrate ”, as recited in claim 3; “ a projection of the first portion projected on the substrate fully overlaps a projection of the gate layer projected on the substrate ”, as recited in claim 4 (note: Figs. 2, and 4-9 only show a cross-sectional view of stacked layers) . The following is a quotation of 35 U.S.C. 112(b): (b ) CONCLUSION.— The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the appl icant regards as his invention. Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claimed limitation of "two outer sides of the two second portions", as recited in claim 1, is unclear as to whether said limitation is in one-to-one or multiple-to-one relationship betwee n the “outer side” and the “second portion” applicant refers . The claimed limitation of " a PN structure therebetween ", as recited in claim 1 , is unclear as to which element s the term "there between " applicant refers. The claimed limitation of "the source-drain contacting layer contacts the third portions and the fourth portion through the holes", as recited in claim 16, is unclear as to i) how the (a single) source-drain contacting layer contacts and the fourth portion “through the holes”; and ii) whether the source-drain contacting layer contacts each, one or all of the third portions and the fourth portion or applicant refers. The claimed limitations of "a passivation layer, disposed on the source-drain contacting layer away and the interlayer insulating layer", as recited in claim 17, are unclear as to i) which element(s) that “a passivation layer” disposed on; and ii) as to which element away from which element applicant refers. The claimed limitation of "projections of the two second portions", as recited in claims 9 and 10, is unclear as to whether said limitation is in one-to-one or multiple-to-one relationship between the “projection” and the “second portion” applicant refers. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1, 4- 7 , 11, 13-20, as best understood, is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yamazaki et al. (6,639,244) . As for claim 1, Yamazaki et al. show in Fig. 1 and related text a display panel, comprising: a substrate 101; and a thin film transistor (TFT) (driver circuit), disposed on the substrate and comprising: a polysilicon layer 1 03 -109 ( C ol. 8, line 1) , disposed on the substrate and comprising: a first portion 106 ; two second portions 105 , disposed on two opposite sides of the first portion; two third portions 103/104 , disposed on two outer sides of the two second portions away from the first portion; and a fourth portion 108 , disposed on one of the two third portions to define a PN structure therebetween; a gate layer 119 , disposed on the substrate and corresponding to the first portion; and a source-drain contacting layer 125/126/ 127 , disposed on the gate layer and electrically contacting the fourth portion and the two third portions. As for claim 4 , Yamazaki et al. show a projection of the first portion projected on the substrate fully overlaps a projection of the gate layer projected on the substrate (Fig. 1) . As for claim 5 , Yamazaki et al. show the first portion is a non-doped portion, and the two second portions, the two third portions, and the fourth portion are doped portions; and a doping type of the two third portions is same with a doping type of the two second portions, and is different from a doping type of the fourth portion (Col. 5, lines 25-29) . As for claim 6 , Yamazaki et al. show the two second portions are N-type lightly doped portions, the two third portions are N-type heavily portions, and the fourth portion is a P-type doped portion (Col. 5, lines 25-29) . As for claim 7, Yamazaki et al. show a light shielding layer 132 , disposed on a side of the substrate facing the polysilicon layer, and comprising: a first light shielding portion, wherein the PN structure is located above the first light shielding portion ( Col. 7, lines 2-6 ) . As for claim 11 , Yamazaki et al. show an insulating layer 102 , disposed on the substrate, wherein the polysilicon layer is disposed on the insulating layer (Fig. 1) . As for claim 13 , Yamazaki et al. show a gate insulating layer 117 , disposed between the polysilicon layer and the gate layer (Fig. 1) . As for claim 14 , Yamazaki et al. show the gate layer is disposed on a side of the polysilicon layer away from the substrate (Fig. 1) . As for claim 15 , Yamazaki et al. show an interlayer insulating layer 124 , disposed between the gate insulating layer and the source-drain contacting layer, and covering the gate layer (Fig. 1) . As for claim 16 , Yamazaki et al. show the interlayer insulating layer is provided with a plurality of holes, and the source-drain contacting layer contacts the third portions and the fourth portion through the holes (Fig. 1) . As for claim 17 , Yamazaki et al. show a passivation layer 130/131/133 , disposed on the source-drain contacting layer away and the interlayer insulating layer (Fig. 1) . As for claim 18 , Yamazaki et al. show a surface of the fourth portion facing the source-drain contacting layer and a surface of another one of the two third portions facing the source-drain contacting layer are flush (Fig. 1) . As for claim 19 , Yamazaki et al. show the polysilicon layer is integrated (Fig. 1) . As for claim 20 , Yamazaki et al. show the substrate is a glass substrate (Col. 5, lines 5-11) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claim (s) 2 and 3, as best understood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (6,639,244) in view of Liu et al. (8,076,195) . As for claims 2-3, Yamazaki et al. disclosed substantially the entire claimed invention, as applied to claim 1 above, except the fourth portion is disposed on a surface of the one of the two third portions facing the source-drain contacting layer (claim 2) ; and a projection of the fourth portion projected on the substrate is located within a projection of the one of the two third portions projected on the substrate (claim 3) . Liu et al. teach in Figs. 4C, 4D, 5A and related text: As for claim 2, the fourth portion 660 is disposed on a surface of the one of the two third portions N++ facing the source-drain contacting layer METAL 1. As for claim 3, a projection of the fourth portion projected on the substrate (not shown) is located within a projection of the one of the two third portions projected on the substrate (Figs. 4C, 4D and 5A) . Yamazaki et al. and Liu et al. are analogous art because they are directed to a transistor and one of ordinary skill in the art would have had a reasonable expec tation of success to modify Yamazaki et al. with the specified feature ( s ) of Liu et al. because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include the fourth portion being disposed on a surface of the one of the two third portions facing the source-drain contacting layer; and a projection of the fourth portion projected on the substrate being located within a projection of the one of the two third portions projected on the substrate , as taught by Liu et al., in Yamazaki et al.'s device, in order to reduce size of the device. Claim (s) 8 -10 and 12, as best under s tood, is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamazaki et al. (6,639,244) in view of Murade ( 200 1 /00 1 9 384 ) . As for claims 8-10, Yamazaki et al. show disclosed substantially the entire claimed invention, as applied to claim 7 above, including the light shielding layer further comprises: a second light shielding portion, spaced apart from the first light shielding portion ( Fig. 1; Col. 7, lines 2-6 ) ; an insulating layer 102 , disposed on the substrate, wherein the polysilicon layer is disposed on the insulating layer (Fig. 1) . Yamazaki et al. does not disclose a projection of the fourth portion projected on the substrate overlaps a projection of the first light shielding portion projected on the substrate (claim 8); a projection of the first light shielding portion projected on the substrate overlaps a projection of the fourth portion projected on the substrate, and a projection of the second light shielding portion projected on the substrate overlaps projections of the two second portions projected on the substrate (claim 9); a projection of the second light shielding portion projected on the substrate overlaps projections of the two second portions projected on the substrate (claim 10); and the insulating layer covering the light shielding layer (claim 12). Murade teaches in Fig s . 35A-35B and related text: As for claim 8, a projection of the fourth portion (drain region of 46 ) projected on the substrate overlaps a projection of the first light shielding portion ( left one of) 7 projected on the substrate . As for claim s 9 and 10 , a projection of the first light shielding portion ( left one of) 7 projected on the substrate overlaps a projection of the fourth portion (drain region of) 46 projected on the substrate, and a projection of the second light shielding portion (right one of) 7 projected on the substrate overlaps projections of the two second portions LDD of 47 projected on the substrate. As for claim 12, an insulating layer 10 , disposed on the substrate and covering the light shielding layer, wherein the polysilicon layer is disposed on the insulating layer . Yamazaki et al. and Murade are analogous art because they are directed to a transistor and one of ordinary skill in the art would have had a reasonable expec tation of success to modify Yamazaki et al. with the specified feature ( s ) of Murade because they are from the same field of endeavor. It would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention to include a projection of the fourth portion projected on the substrate overlap ping a projection of the first light shielding portion projected on the substrate; a projection of the first light shielding portion projected on the substrate overlap ping a projection of the fourth portion projected on the substrate, and a projection of the second light shielding portion projected on the substrate overlap ping projections of the two second portions projected on the substrate; a projection of the second light shielding portion projected on the substrate overlap ping projections of the two second portions projected on the substrate; and the insulating layer covering the light shielding layer , as taught by Murade , in Yamazaki et al. ’s device, in order to effectively reduce photo leakage current in the active layer and improve the performance of the device. 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