DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
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Status of claim(s) to be treated in this office action:
Independent: 1, 9 and 15.
Pending: 1-20.
Withdrawn: 15-20
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5 and 8-14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Chen US Pg Pub. 20100224966 A1; in view of Yu et al., US PG pub. 20130207239 A1.
Re: Independent Claim 1, Chen discloses a chip (108, fig. 7);
a redistribution layer (152, fig. 6j), disposed on the chip (108, fig. 7) and electrically connected with the chip (108, fig. 7), wherein the redistribution layer (152, fig. 6j) includes a metallization layer (flat metal layer 152, fig. 6j) and a dielectric material layer (156, fig. 6i) disposed on and covering the metallization layer (flat metal layer 152, fig. 6j), the metallization layer (flat metal layer 152, fig. 6j) includes first contact pads (right side contacts 152, fig. 6i, 6j and 7) and the dielectric material layer (156, fig. 6i) has openings exposing the first contact pads (right side contacts 152, fig. 6i, 6j and 7); and
first under-ball metallurgies patterns (right side 155 and 165, fig. 6i and 6j and 7), disposed over the openings and on the first contact pads (right side contacts 152, fig. 6i, 6j and 7).
Chen is silent regarding: wherein the first under-ball metallurgy patterns (right side 155 and 165, fig. 6i and 6j and 7) extend on and contact sidewalls and top surfaces of the first contact pads (right side contacts 152, fig. 6i, 6j and 7).
Yu teaches the first under-ball metallurgy patterns (113, fig. 6B) extend on and contact sidewalls and top surfaces of the first contact pads (109, fig. 6B).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include side surface contact with the contact pads since this can increase contact area between UBM pattern and contact pad thereby improving lower contact resistance with better current distribution and improve mechanical anchoring.
Re: Claim 2, Chen and Yu discloses all the limitations of claim 1 on which this claim depends. Chen further discloses: wherein the metallization layer (flat metal layer 152, fig. 6j) further comprises second contact pads (left side contacts 152, fig. 6i, 6j and 7) exposed by the openings, the second contact pads (left side contacts 152, fig. 6i, 6j and 7) are located closer to an outer edge of the semiconductor package than the first contact pads (right side contacts 152, fig. 6i, 6j and 7).
Re: Claim 3, Chen and Yu discloses all the limitations of claim 2 on which this claim depends. Chen further discloses: second under-ball metallurgies patterns (left side 155 and 165, fig. 6i and 6j and 7; as shown in figure 7 there can be multiple of UBM patterns) disposed on the second contact pads (left side contacts 152, fig. 6i, 6j and 7) and extending on and contacting top surfaces of the second contact pads (left side contacts 152, fig. 6i, 6j and 7).
Re: Claim 4, Chen and Yu discloses all the limitations of claim 3 on which this claim depends. Chen further discloses: wherein the second under-ball metallurgies patterns (left side 155 and 165, fig. 6i and 6j and 7; as shown in figure 7 there can be multiple of UBM patterns) extend entirely on the top surfaces of the second contact pads (left side contacts 152, fig. 6i, 6j and 7).
Re: Claim 5, Chen and Yu discloses all the limitations of claim 3 on which this claim depends. Chen further discloses: wherein the second under-ball metallurgies patterns (left side 155 and 165, fig. 6i and 6j and 7; as shown in figure 7 there can be multiple of UBM patterns) extend on portions of the top surfaces of the second contact pads (left side contacts 152, fig. 6i, 6j and 7), and the dielectric material layer (156, fig. 6i) extends on remaining portions of the top surfaces of the second contact pads (left side contacts 152, fig. 6i, 6j and 7).
Re: Claim 8, Chen and Yu discloses all the limitations of claim 1 on which this claim depends. Chen further discloses: wherein the first contact pads (right side contacts 152, fig. 6i, 6j and 7) are distributed within a span of the chip (108, fig. 7).
Re: Independent Claim 9, Chen discloses a chip (108, fig. 7);
a redistribution layer (152, fig. 6j), disposed on the chip (108, fig. 7) and electrically connected with the chip (108, fig. 7), wherein the redistribution layer (152, fig. 6j) includes a metallization layer (flat metal layer 152, fig. 6j) and a dielectric material layer (156, fig. 6i) disposed on and covering the metallization layer (flat metal layer 152, fig. 6j), the metallization layer (flat metal layer 152, fig. 6j)
includes first contact pads (right side contacts 152, fig. 6i, 6j and 7) and first routing traces (right side of 145, fig. 6i, 6j and 7) connected to the first contact pads (right side contacts 152, fig. 6i, 6j and 7) and the dielectric material layer (156, fig. 6i) has openings exposing the first contact pads (right side contacts 152, fig. 6i, 6j and 7); and
first under-ball metallurgies patterns (right side 155 and 165, fig. 6i and 6j and 7), disposed over the openings and on the first contact pads (right side contacts 152, fig. 6i, 6j and 7).
Chen is silent regarding: wherein the first under-ball metallurgy patterns (right side 155 and 165, fig. 6i and 6j and 7) extend on and contact sidewalls and top surfaces of the first contact pads (right side contacts 152, fig. 6i, 6j and 7).
Yu teaches the first under-ball metallurgy patterns (113, fig. 6B) extend on and contact sidewalls and top surfaces of the first contact pads (109, fig. 6B).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include side surface contact with the contact pads since this can increase contact area between UBM pattern and contact pad thereby improving lower contact resistance with better current distribution and improve mechanical anchoring.
Re: Claim 10, Chen and Yu discloses all the limitations of claim 9 on which this claim depends. Chen further discloses: wherein the metallization layer (flat metal layer 152, fig. 6j) further comprises second contact pads (left side contacts 152, fig. 6i, 6j and 7) exposed by the openings and second routing traces (left side of 145, fig. 6i, 6j and 7) connected to the second contact pads (left side contacts 152, fig. 6i, 6j and 7), the second contact pads (left side contacts 152, fig. 6i, 6j and 7) are located closer to an outer edge of the semiconductor package than the first contact pads (right side contacts 152, fig. 6i, 6j and 7).
Re: Claim 11, Chen and Yu discloses all the limitations of claim 10 on which this claim depends. Chen further discloses: second under-ball metallurgies patterns (left side 155 and 165, fig. 6i and 6j and 7; as shown in figure 7 there can be multiple of UBM patterns) disposed on the second contact pads (left side contacts 152, fig. 6i, 6j and 7), and the second under-ball metallurgies patterns (left side 155 and 165, fig. 6i and 6j and 7; as shown in figure 7 there can be multiple of UBM patterns) extend entirely on the top surfaces of the second contact pads (left side contacts 152, fig. 6i, 6j and 7).
Re: Claim 12, Chen and Yu discloses all the limitations of claim 10 on which this claim depends. Chen further discloses: wherein the metallization layer (flat metal layer 152, fig. 6j) further comprises third contact pads (middle region 152, fig. 6i, 6j and 7) and third routing traces connected to the third contact pads (middle region 152, fig. 6i, 6j and 7), and the third contact pads (middle region 152, fig. 6i, 6j and 7) are located closer to the outer edge of the semiconductor package than the first contact pads (right side contacts 152, fig. 6i, 6j and 7) and the second contact pads (left side contacts 152, fig. 6i, 6j and 7).
Re: Claim 13, Chen and Yu discloses all the limitations of claim 12 on which this claim depends. Chen further discloses: third under-ball metallurgies patterns (middle region of 155 and 165, fig. 6i and 6j and 7) disposed on the third contact pads (middle region 152, fig. 6i, 6j and 7), wherein the third under-ball metallurgies patterns (155 and 165, fig. 6i and 6j and 7) extend on portions of the top surfaces of the third
contact pads, and the dielectric material layer (156, fig. 6i) extends on remaining portions of the top surfaces of the third contact pads (middle region 152, fig. 6i, 6j and 7).
Re: Claim 14, Chen and Yu discloses all the limitations of claim 12 on which this claim depends. Chen further discloses: wherein the first contact pads (right side contacts 152, fig. 6i, 6j and 7), the second contact pads (left side contacts 152, fig. 6i, 6j and 7) and the third contact pads (middle region 152, fig. 6i, 6j and 7) are respectively arranged in concentric ring shapes around a periphery of the chip (108, fig. 7).
Below an annotated figure 7 for Chen et al., US PG pub. 20100224966 A1.
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Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Lin et al., US PG pub. 20190139784 A1”) Discloses a package structure including a semiconductor die, a redistribution layer and a plurality of conductive elements is provided. At least one joint of the joints in the redistribution layer or on the semiconductor die is connected with the conductive element for electrically connecting the redistribution layer, the semiconductor die and the conductive elements.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5 and 8-14 have been considered but are moot in view of the new ground(s) of rejection in view of Yu et al., US PG pub. 20130207239 A1.
Allowable Subject Matter
Claim(s) 6-7 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Re: Claim 6 (Claim 7 is dependent to Claim 6), the prior art of record do not disclose or suggest, in combination with all other limitations in the claim: wherein the metallization layer further includes first routing traces connected to the first contact pads, the first contact pads have elliptical spans, and extending directions of the first routing traces are along major axes of the elliptical and along a radial inward direction towards the chip.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on 9-5PM EST.
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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