DETAILED ACTION
This Office Action is sent in response to Applicant’s Communication received 29 Nov 2023 for application number 18/522,276. The Office hereby acknowledges receipt of the following and placed of record in file: Specification, Drawings, Abstract, Oath/Declaration, and Claims.
Claims 1-14 presented for examination. Elected claims 1-2, 4, and 8-14 are examined below. Non-elected claims 3 and 5-7 have been withdrawn.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 29 Nov 2023 was filed before the mailing of this Office Action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Election/Restrictions
Applicant’s election without traverse of claims 1-2, 4, and 8-14, drawn to Device Embodiment I. in the reply filed on 23 Mar 2026 is acknowledged.
Claims 3 and 5-7 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 23 Mar 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 11-12 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 11-12, where applicant acts as his or her own lexicographer to specifically define a term of a claim contrary to its ordinary meaning, the written description must clearly redefine the claim term and set forth the uncommon definition so as to put one reasonably skilled in the art on notice that the applicant intended to so redefine that claim term. Process Control Corp. v. HydReclaim Corp., 190 F.3d 1350, 1357, 52 USPQ2d 1029, 1033 (Fed. Cir. 1999). The term “dummy gate electrode” in claim 11 is used by the claim to mean “an electrically functioning electrode,” while the accepted meaning of a “dummy” structure is a structure that is “non-functional.” The term is indefinite because the specification does not clearly redefine the term.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 4, and 8-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. [hereinafter as Lee] (US 2012/0299094 A1) in view of Nakagawa et al. [hereinafter as Nakagawa] (US 2020/0243641 A1).
In reference to claim 1, Lee teaches A semiconductor device, comprising:
a semiconductor layer [N-type pillars 110N of blocking layer 110; Fig. 3, para 0063] having a first conductivity type [N-type] and including a first surface [top surface of 110] and a second surface [bottom surface of 110] on an opposite side of the first surface;
a plurality of element structures [source region 150/P-type well 160/P-type impurity region 162; Fig. 3, paras 0067-0068] formed in the first surface of the semiconductor layer [110N] at equal intervals in one direction [x-direction; Fig. 3]; and
a super junction structure [super junction 100; Fig. 3, para 0053] formed in the semiconductor layer [110N],
wherein each of the plurality of element structures [150/160/162/110P] includes:
a body region [P-type well 160; Fig. 3, para 0067] having a second conductivity type [P-type] and formed in the first surface [top surface of 110] of the semiconductor layer [110N]; and
a first region [source region 150; Fig. 3, para 0067] having the first conductivity type [N-type] and formed in a surface of the body region [110P/160],
wherein the super junction structure [100] includes a plurality of column layers [P-type pillars 110P; Fig. 3, para 0063] having the second conductivity type [P-type] formed in the semiconductor layer [110N] at equal intervals in the one direction [x-direction] and extending in a thickness direction [into and out of the page of Fig. 3, as can be seen in Fig. 2B] of the semiconductor layer [110N].
However, Lee does not explicitly teach:
wherein an inter-body region pitch, which is an arrangement interval of the body regions of the plurality of element structures in the one direction, is different from an inter-column layer pitch, which is an arrangement interval of the plurality of column layers in the one direction.
Lee and Nakagawa teach:
wherein an inter-body region pitch [inter-body region pitch; see annotated Fig. 52 of Nakagawa below], which is an arrangement interval of the body regions [body regions 426; Fig. 52, para 1019 of Nakagawa; analogously, 160 of Lee] of the plurality of element structures [150/160/162 of Lee] in the one direction [x-direction of Lee], is different from an inter-column layer pitch [inter-column layer pitch; see annotated Fig. 52 of Nakagawa below], which is an arrangement interval of the plurality of column layers [p-type deep well regions 455; Fig. 52, para 1089 of Nakagawa; analogously, 110P of Lee] in the one direction [x-direction of Lee].
It would have been obvious to one of ordinary skill in art, absent unexpected results, having the teachings of Lee and Nakagawa before the effective filing date of the claimed invention, to include the different pitches as disclosed by Nakagawa into the semiconductor device of Lee in order to obtain a super junction with varying pitches.
One of ordinary skill in the art would be motivated to obtain a barrier and pillar regions in a IGBT semiconductor device to provide the predictable result of improving electric field uniformity, balancing breakdown capability with low on-resistance, and providing manufacturing flexibility.
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In reference to claim 2, Lee and Nakagawa teach the invention of claim 1.
Nakagawa teaches The semiconductor device of Claim 1, wherein the inter-body region pitch is shorter than the inter-column layer pitch [inter-body region pitch is smaller than inter-column layer pitch; see annotated Fig. 52 above].
In reference to claim 4, Lee and Nakagawa teach the invention of claim 1.
Lee teaches The semiconductor device of Claim 1, wherein the plurality of column layers [110P] include a column layer [110P below 160] disposed below the body region [160] to be in contact with the body region [160].
In reference to claim 8, Lee and Nakagawa teach the invention of claim 1.
Lee teaches The semiconductor device of Claim 1, further comprising: a first electrode [gate electrode 170; Fig. 3, para 0069] disposed on the first surface [top surface of 110] of the semiconductor layer [110N] and electrically connected to the first region [150] and the body region [160].
In reference to claim 9, Lee and Nakagawa teach the invention of claim 1.
Lee teaches The semiconductor device of Claim 1, further comprising: a gate insulating film [gate oxide layer 172; Fig. 3, para 0069] formed in the first surface [top surface of 110] of the semiconductor layer [110N] and arranged to straddle two body regions [160] of the body regions [160] adjacent to each other in the one direction [x-direction]; and a gate electrode [170] formed on the gate insulating film [172].
In reference to claim 10, Lee and Nakagawa teach the invention of claim 9.
Lee teaches The semiconductor device of Claim 9, wherein the gate electrode [170] includes: a first portion [portion of 170 extending in the x-direction] extending in the one direction [x-direction] in a plan view [Fig. 2B, although 170 not shown]; a second portion [portion of 170 extending in the vertical direction of Fig. 2B] extending in a direction perpendicular [vertical direction of Fig. 2B] to the one direction [x-direction (i.e. horizontal direction of Fig. 2B)]; and an intersection portion where the first portion and the second portion intersect [the first and second portions of 170 would intersect; Fig. 2B, although 170 not shown].
In reference to claim 11, Lee and Nakagawa teach the invention of claim 1.
Lee teaches The semiconductor device of Claim 1, further comprising: at least one insulating film formed in the first surface [top surface of 110] of the semiconductor layer [110N] and arranged to straddle two body regions [160] of the body regions [160] adjacent to each other in the one direction [x-direction], wherein the at least one insulating film includes a first insulating film [172] and a second insulating film [insulating layer 174/176; Fig. 3, para 0070] which are alternately formed in the one direction [x-direction] with the body region [160] interposed between the first insulating film [172] and the second insulating film [174/176], wherein a gate electrode [170] is formed on the first insulating film [172], and wherein a dummy gate electrode [source electrode 180; Fig. 3, para 0071] electrically connected to a first electrode [170] is formed on the second insulating film [174/176].
In reference to claim 12, Lee and Nakagawa teach the invention of claim 11.
Lee teaches The semiconductor device of Claim 11, wherein the gate electrode [170] has a band shape extending in a direction perpendicular [vertical direction in Fig. 2B] to the one direction [x-direction (horizontal direction of Fig. 2B)] in a plan view [Fig. 2B], and wherein the dummy gate electrode [180] has a band shape extending in a direction perpendicular [vertical direction in Fig. 2B] to the one direction [x-direction (horizontal direction of Fig. 2B)] in a plan view [Fig. 2B].
In reference to claim 13, Lee and Nakagawa teach the invention of claim 1.
Lee teaches The semiconductor device of Claim 1, wherein each of the plurality of column layers [110P] includes a concave and convex side surface formed by repeatedly arranging a convex portion and a concave portion in the thickness direction of the semiconductor layer [Fig. 3 depicts 110P with concave and convex side surfaces].
In reference to claim 14, Lee and Nakagawa teach the invention of claim 1.
Lee teaches The semiconductor device of Claim 1, wherein each of the plurality of element structures [150/160/162] includes a planar gate structure [gate stack 172/170].
Examiner’s Note
The prior art made of record and not relied upon is considered pertinent to Applicant's disclosure as follows. Applicant is reminded that in amending in response to a rejection of claims, the patentable novelty must be clearly shown in view of the state of the art disclosed by the references cited and the objections made. Applicant must also show how the amendments avoid such references and objections. See 37 CFR § 1.111(0).
Dai et al. (US- 20220367616-A1), Jun et al. (US- 9190469-B2), Lin et al. (US- 20120199903-A1), Mori et al. (US- 20190371885-A1), Nagata (US- 20230178604-A1), Privat et al. (US- 20230061047-A1), and Sasaki (US- 20100187599-A1) disclose super junction structures.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW CHUNG whose telephone number is (571)272-5237. The examiner can normally be reached M-F 9-5pm.
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/ANDREW CHUNG/
Examiner, Art Unit 2898
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