Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
This office action is in response to applicant’s communication filed on 11/29/23. Claims 1-10 are pending in this application.
Claim Rejections Under 35 U.S.C. §103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-10 are rejected under 35 U.S.C. 103 as being unpatentable over US Patent Application Publication No. 2017/0184893 (hereinafter “US '893”) in view of Chinese Patent Application Publication No. CN 101964309 A (hereinafter “CN '309”).
Regarding Claim 1, US '893 discloses a panel structure, comprising:
a glass substrate (11) having a first surface (see paragraphs [0052]-[0061]; Fig. 3);a first insulating layer (14) on the first surface;a semiconductor device layer (oxide semiconductor film 13) on the first insulating layer, wherein the semiconductor device layer comprises a first device part (first oxide semiconductor film 13A) and a second device part (second oxide semiconductor film 13B), a region (50) occupied by the first device part corresponds to a display area of the panel structure, and a region (60) occupied by the second device part corresponds to a peripheral driving circuit area of the panel structure;wherein the semiconductor device layer is made of a first material (indium gallium zinc oxide, IGZO).US '893 does not explicitly disclose a second insulating layer between the first device part and the first insulating layer, wherein the second insulating layer coincides with the first device part in a direction perpendicular to a thickness of the glass substrate, nor does it disclose that the second insulating layer is made of a second material having an energy band gap less than the energy band gap of the first material.
However, CN '309 discloses a display panel structure comprising a light-blocking material layer (120b, equivalent to the claimed second insulating layer) disposed between an oxide channel layer (110a, equivalent to the semiconductor device layer) and a gate insulating layer (GI, equivalent to the first insulating layer) (see paragraphs [0034]-[0082]; Figs. 1-6). CN '309 teaches that the oxide channel layer is formed of a first material (IGZO) and the light-blocking material layer is formed of a second material (titanium oxide) to prevent ultraviolet light from influencing the semiconductor layer. CN '309 further teaches using the same mask for patterning the oxide channel layer and the light-blocking material layer, such that they completely coincide in the thickness direction of the substrate. It is well known in the art, based on the inherent properties of these materials, that the band gap of titanium oxide is less than the band gap of IGZO.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the panel structure of US '893 by incorporating the light-blocking material layer (second insulating layer) of CN '309 between the first insulating layer and the semiconductor device layer in the display area. The motivation to combine these references would have been to provide an ultraviolet light-blocking material layer to avoid the adverse influence of ultraviolet light on the display area transistor semiconductor layer, as taught by CN '309.
Regarding claim 2, ‘893 and CN ‘309 disclose the panel structure according to claim 1, wherein the first material is indium gallium zinc oxide; and the first insulating layer is made of silicon oxide (see para [0019], disclosing Igzo).
Regarding claim 3, ‘893 and CN ‘309 disclose the panel structure according to claim 2, wherein the second material is any one of titanium dioxide, zinc oxide, indium trioxide, cadmium sulfide, or cadmium selenide (see para [0019], disclosing ZN).
Regarding claim 4, ‘893 and CN ‘309 disclose the panel structure according to claim 1, wherein the panel structure further comprises a first metal layer, and the first metal layer is disposed on the first surface and covers part of the first surface (see elements 15a/b covering part of 11); the first insulating layer covers the first metal layer and part of the first surface not covered by the first metal layer (see 14 covering 15 and 11 ant not at 15); and the semiconductor device layer is disposed in a region of the first insulating layer corresponding to the first metal layer (see 13a/b).
Regarding claim 5, ‘893 and CN ‘309 disclose the panel structure according to claim 4, further comprising a second metal layer, wherein the second metal layer covers a region of the semiconductor device layer corresponding to the first metal layer (see 15a/b covering under 13).
Regarding claim 6, ‘893 and CN ‘309 disclose the panel structure according to claim 5, further comprising a third insulating layer, wherein the third insulating layer covers the second metal layer and a region of the first insulating layer not covered by the second metal layer (see element 19, i.e. fig 6).
Regarding claim 7, ‘893 and CN ‘309 disclose the panel structure according to claim 6, wherein a through hole is defined in a region of the third insulating layer corresponding to the second metal layer (see through hole in 20 in fig 6b), part of the second metal layer is exposed from the through hole(see 18da is exposed); and the panel structure further comprises a conductive layer 23p, the conductive layer is disposed on the third insulating layer, and part of the conductive layer is filled in the through hole and is connected to the second metal layer (see fig 6b filling through hole with 23p).
Regarding Claim 8, US '893 discloses a preparing method of a panel structure, comprising:
providing a glass substrate (11) having a first surface;forming a first metal layer (gate electrode 15), wherein the first metal layer comprises a first circuit structure (first gate electrode 15A) corresponding to a display area (50) and a second circuit structure (second gate electrode 15B) corresponding to a peripheral driving circuit area (60);forming a first insulating layer (gate insulating layer 14) on the first metal layer and part of the first surface not covered by the first metal layer;forming a semiconductor device layer (oxide semiconductor film 13) on the first insulating layer, wherein the semiconductor device layer is made of a first material (IGZO).US '893 does not explicitly disclose depositing a first original metal layer and patterning it to form the first metal layer, nor does it disclose forming a second insulating layer in a region of the first insulating layer corresponding to the first circuit structure, where the second insulating layer is made of a second material having an energy band gap less than the first material.
However, CN '309 teaches forming an ultraviolet light-blocking material (120, second insulating layer) and an oxide semiconductor layer (110) in order on the gate insulating layer (GI), where the light-blocking layer is made of titanium oxide and the semiconductor layer is made of IGZO (having a larger bandgap than titanium oxide). Furthermore, forming a gate metal layer using a deposition and patterning process is a routine, well-known manufacturing choice in the semiconductor arts.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the method of US '893 to include depositing and patterning the metal layer as a standard manufacturing technique, and to form the second insulating layer of CN '309 prior to forming the semiconductor device layer. The motivation to do so would have been to protect the semiconductor layer of the display area transistors from ultraviolet light degradation, as taught by CN '309.
Regarding claim 9, ‘893 and CN ‘309 disclose the preparing method of the panel structure according to claim 8, wherein the forming of the second insulating layer in a region of the first insulating layer corresponding to the first circuit structure comprises: depositing the second insulating layer on the first insulating layer to cover the first insulating layer (see 19 covers 14); coating photoresist in a region of the second insulating layer corresponding to the first circuit structure to form a photoresist layer (see fig 89 and fig 6 disclosing photoresist to form first circuit); removing part of the second insulating layer not coated with the photoresist, and remaining part of the second insulating layer coated with the photoresist, so that the second insulating layer coincide with a region of the first insulating layer corresponding to the first circuit structure (see fig 6b); and removing the photoresist layer on the second insulating layer (see fig 6b disclosing 20 is etched to expose 19).
Regarding claim 10, ‘893 and CN ‘309 disclose the preparing method of the panel structure according to claim 8, further comprising: depositing a second original metal layer on the semiconductor device layer (see 18), and patterning the second original metal layer to form a second metal layer (see fig 6 where 18 is patterned); depositing a third insulating layer on the second metal layer and a region of the first insulating layer not covered by the second metal layer (see 21 is formed on 18); forming a through hole on the third insulating layer to expose part of the second metal layer from the through hole (see hole in 21); and depositing a conductive layer on the third insulating layer, wherein part of the conductive layer is filled in the through hole and is connected to the second metal layer (see 23p formed in through hole).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to EDWARD CHIN whose telephone number is (571)270-1827. The examiner can normally be reached M-F 9AM-5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached at (571) 270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/EDWARD CHIN/Primary Examiner, Art Unit 2893
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