Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
1. Applicant's election, without traverse, of claims 1-10 in the “Response to Restriction Requirement” filed on 04/17/2026 is acknowledged and entered by the Examiner.
This office action consider claims 1-20 pending for prosecution, wherein claims 11-20 are withdrawn from further consideration, and claims 1-10 are presented for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (100; Fig 3A; [0063]) = (element 100; Figure No. 3A; Paragraph No. [0063]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
2. Claims 1-6, 8, and 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Im et al. (US 20160233232 A1; hereinafter Im).
Regarding claim 1, Im teaches a semiconductor device (see the entire document, specifically Fig. 1+; [0002+], and as cited below), comprising:
a substrate (210; Fig. 6; [0074-0075]) including a cell array region (DR; Fig. 6; [0074-0075]) and a connection region (CR; Fig. 6; [0074-0075]);
a stack (ST; Fig. 6; [0076-0077]) including electrodes (227; Fig. 6; [0076-0077]), which are vertically stacked on the substrate (210; Fig. 6; [0074-0075]), and which have a staircase structure in the connection region (CR; Fig. 6; [0074-0077]);
channel regions (VCS; Fig. 6; [0074]) provided on the cell array region (DR; Fig. 6; [0074-0075]) that extend vertically through the stack (ST; Fig. 6; [0076-0077]); and
a planarization insulating layer ({230, 232}; Fig. 6; see [0078-0080, 0089-0091]) that covers the stack (ST; Fig. 6; [0076-0077]) in the connection region (CR; Fig. 6; [0074-0075]), wherein the planarization insulating layer ({230, 232}; Fig. 6; see [0078-0080, 0089-0091]) comprises:
a first insulating layer ({230}; Fig. 6; see [0078-0080, 0089-0091]) in contact with the stack (ST; Fig. 6; [0076-0077]); and
a second insulating layer ({232}; Fig. 6; see [0078-0080, 0089-0091]) that covers the first insulating layer ({230, 232}; Fig. 6; see [0078-0080, 0089-0091]),
wherein the first insulating layer ({230}; Fig. 6; see [0078-0080, 0089-0091]) comprises high-density plasma (HDP) oxide (see [0089], where the first interlayer dielectric 230 may include performing a high-density plasma chemical vapor deposition (HDP CVD) process using a reactive gas containing silane (SiH.sub.4) and oxygen (O.sub.2)), which is doped with first dopants (see [0089], where the first interlayer dielectric 230 may include performing a high-density plasma chemical vapor deposition (HDP CVD) process using a reactive gas containing silane (SiH.sub.4) and oxygen (O.sub.2)), and
wherein the second insulating layer ({232}; Fig. 6; see [0078-0080, 0089-0091]) comprise tetraethyl orthosilicate (TEOS) oxide (see [0091], where the second interlayer dielectric 232 may include performing a plasma enhanced chemical vapor deposition (PE CVD) process using a reactive gas containing tetraethoxysilane (TEOS), oxygen (O.sub.2), and/or nitrous oxide (N.sub.2O)), which is doped with second dopants (see [0091], where the second interlayer dielectric 232 may include performing a plasma enhanced chemical vapor deposition (PE CVD) process using a reactive gas containing tetraethoxysilane (TEOS), oxygen (O.sub.2), and/or nitrous oxide (N.sub.2O)).
Regarding claim 2, Im teaches all of the features of claim 1.
Im further teaches wherein the first dopants comprise boron (B), phosphorus (P), carbon (C), nitrogen (N), or silicon (Si) (see [0089], silicon, see where the first interlayer dielectric 230 may include performing a high-density plasma chemical vapor deposition (HDP CVD) process using a reactive gas containing silane (SiH.sub.4) and oxygen (O.sub.2)), and wherein the second dopants comprise boron (B), phosphorus (P), carbon (C), nitrogen (N), or silicon (Si) (see [0091], nitrogen, see where the second interlayer dielectric 232 may include performing a plasma enhanced chemical vapor deposition (PE CVD) process using a reactive gas containing tetraethoxysilane (TEOS), oxygen (O.sub.2), and/or nitrous oxide (N.sub.2O)).
Regarding claim 3, Im teaches all of the features of claim 1.
Im further teaches wherein the second insulating layer ({232}; Fig. 6; see [0078-0080, 0089-0091]) is spaced apart from the stack by the first insulating layer ({230}; Fig. 6; see [0078-0080, 0089-0091]) .
Regarding claim 4, Im teaches all of the features of claim 1.
Im further teaches wherein the first insulating layer ({230}; Fig. 6; see [0078-0080, 0089-0091]) covers and conforms to the staircase structure of the stack (ST; Fig. 6).
Regarding claim 5, Im teaches all of the features of claim 1.
Im further teaches wherein an interface between the first insulating layer ({230}; Fig. 6; see [0078-0080, 0089-0091]) and the second insulating layer ({232}; Fig. 6; see [0078-0080, 0089-0091]) has a wavy shape.
Regarding claim 6, Im teaches all of the features of claim 1.
Im further teaches wherein a thickness of the first insulating layer ({230}; Fig. 6; see [0078-0080, 0089-0091]) is greater than a thickness of one stepped portion (in view of the bottommost step of ST; see Fig. 6) of the staircase structure of the stack (ST; see Fig. 6).
Regarding claim 8, Im teaches all of the features of claim 1.
Im further teaches wherein a density of the first insulating layer ({230}; Fig. 6; see [0078-0080, 0089-0091], forming the first interlayer dielectric 230 may include performing a high-density plasma chemical vapor deposition (HDP CVD) process) is higher than a density of the second insulating layer ({232}; Fig. 6; see [0078-0080, 0089-0091], forming the second interlayer dielectric 232 may include performing a plasma enhanced chemical vapor deposition (PE CVD) process).
Furthermore, as per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Im teaches the structure of claim 8 as detailed above. Thus, Im teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent.
Regarding claim 10, Im teaches all of the features of claim 1.
Im further comprising: penetration plugs (240; Fig. 6; [0080]), which are provided on the connection region (CR; Fig. 6; [0074-0075]) and extend vertically through the planarization insulating layer ({230, 232}; Fig. 6; see [0078-0080, 0089-0091]) and are connected to the electrodes (227; Fig. 6; [0076-0077]); and interconnection patterns (PAD1; Fig. 6; [0080]), which are on the planarization insulating layer ({230, 232}; Fig. 6; see [0078-0080, 0089-0091]) and are connected to the penetration plugs, wherein the stack (ST; Fig. 6) further comprises insulating patterns (225; Fig. 6; [0076-0077]) interposed between the electrodes (227; Fig. 6; [0076-0077]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
3. Claim 7 is rejected under 35 U.S.C.103 as being unpatentable over Im et al. (US 20160233232 A1; hereinafter Im), in view of the following statement.
Regarding claim 7, Im teaches all of the features of claim 1.
Im further teaches wherein (see below for “an etch rate of”) the first insulating layer ({230}; Fig. 6; see [0078-0080, 0089-0091]) (see below for “is equal or similar to”) (see below for “an etch rate of”) of the second insulating layer ({232}; Fig. 6; see [0078-0080, 0089-0091]).
As noted above, Im does not expressly disclose “wherein an etch rate of the first insulating layer is equal or similar to an etch rate of the second insulating layer”.
However, the reference to the language in claim 7 referring to wherein an etch rate of the first insulating layer is equal or similar to an etch rate of the second insulating layer, it is important to note that “Even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). Accordingly the limitation " wherein an etch rate of the first insulating layer is equal or similar to an etch rate of the second insulating layer " is not patentable over prior art as the structure of the prior art cannot be differentiate from the structural limitation as claimed.
Therefore, in reference to the language in claim 7 referring to wherein an etch rate of the first insulating layer is equal or similar to an etch rate of the second insulating layer, it is noted that Im teaches all the structural elements in claim 7 according to the instant invention and that wherein an etch rate of the first insulating layer is equal or similar to an etch rate of the second insulating layer does not affect the structure of the final device.
Moreover, as per MPEP 2112.01.I guideline, where the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977). In this case, Im teaches the structure of claim 7 as detailed above. Thus, Im teaches all of the structural elements of the claimed product, and when the structure recited in a reference is substantially identical to that of the claims, claimed properties or functions are presumed to be inherent.
4. Claim 9 is rejected under 35 U.S.C.103 as being unpatentable over Im et al. (US 20160233232 A1; hereinafter Im), in view of Yun et al. (US 20150287710 A1; hereinafter Yun).
Regarding claim 9, Im teaches all of the features of claim 1.
Im further teaches wherein the planarization insulating layer ({230, 232}; Fig. 6; see [0078-0080, 0089-0091]) further comprises: a third insulating layer (242; Fig. 6; [0080, 0100] in view of [0078-0080, 0089-0091]) on the second insulating layer ({232}; Fig. 6; see [0078-0080, 0089-0091]); and a fourth insulating layer (250; Fig. 6; [0084, 0103] in view of [0078-0080, 0089-0091]) covering the third insulating layer (242; Fig. 6; see [0080]), wherein the third insulating layer (242; Fig. 6; [0080, 0100] in view of [0078-0080, 0089-0091]) (see below for “comprises high-density plasma (HDP) oxide or silica glass, which is doped with the first dopants”), and wherein the fourth insulating layer (250; Fig. 6; [0084, 0103] in view of [0078-0080, 0089-0091]) (see below for “comprises tetraethyl orthosilicate (TEOS) oxide, which is doped with the second dopants”).
As noted above, Im does not expressly disclose “wherein the third insulating layer comprises high-density plasma (HDP) oxide or silica glass, which is doped with the first dopants, and wherein the fourth insulating layer comprises tetraethyl orthosilicate (TEOS) oxide, which is doped with the second dopants”.
However, in the analogous art, Yun teaches semiconductor devices ([Abstract]), wherein (Fig. 1+; [0003+]) insulating layer (127; Fig. 3; [0047]) and upper interlayer insulating layer (128; Fig. 3; [0047]), upper interlayer insulating layer (147; Fig. 3; [0047]), and upper interlayer insulating layer (162; Fig. 3; [0047]) may include at least one of high density plasma (HDP) oxide, tetra-ethyl-ortho-silicate (TEOS), plasma enhanced TEOS (PE-TEOS), O.sub.3-TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluoride silicate glass (FSG), spin-on-glass (SOG), tonen silazene (TOSZ), or a combination thereof.
It would have been obvious to one with ordinary skill in the art, before the effective filing date of the claimed invention, to modify Im’s insulating layer composition with Yun’s insulating layer composition, and thereby, modified Im’s (by Yun) device will have wherein the third insulating layer (Im 242; Fig. 6; [0080, 0100] in view of [0078-0080, 0089-0091] in view of Yun 147; Fig. 3; [0047]) comprises high-density plasma (HDP) oxide or silica glass, which is doped with the first dopants (Im 242; Fig. 6; [0080, 0100] in view of [0078-0080, 0089-0091] in view of Yun 147; Fig. 3; [0047]), and wherein the fourth insulating layer (Im 250; Fig. 6; [0084, 0103] in view of [0078-0080, 0089-0091] in view of Yun 162; Fig. 3; [0047]) comprises tetraethyl orthosilicate (TEOS) oxide, which is doped with the second dopants (Im 250; Fig. 6; [0084, 0103] in view of [0078-0080, 0089-0091] in view of Yun 162; Fig. 3; [0047]).
The ordinary artisan would have been motivated to modify Im in the manner set forth above, at least, because this inclusion provides insulating layers comprising of at least one of high density plasma (HDP) oxide, tetra-ethyl-ortho-silicate (TEOS), plasma enhanced TEOS (PE-TEOS), O.sub.3-TEOS, undoped silicate glass (USG), phosphosilicate glass (PSG), borosilicate glass (BSG), borophosphosilicate glass (BPSG), fluoride silicate glass (FSG), spin-on-glass (SOG), tonen silazene (TOSZ), or a combination thereof. (Yun [0047]), which helps increase the insulative properties of the insulating layers and increase the protection and functionality of the device.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Omar Mojaddedi whose telephone number is 313-446-6582. The examiner can normally be reached on Monday – Friday, 8:00 a.m. to 4:00 p.m..
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/OMAR F MOJADDEDI/Examiner, Art Unit 2898
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