Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The previous Non-Final Office Action submitted on August 13, 2025 is withdrawn/superseded.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 29, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Response to Amendment
The Amendment filed November 13, 2025 has been entered. Claims 1-12 remain pending in the application. No amendments have been made to the claims set forth in the Non-Final Office Action mailed August 13, 2025; hereafter referred to as the Non-Final Office Action.
Response to Arguments
Applicant’s arguments, see pages 7-15 of applicant’s remarks, filed November 13, 2025, with respect to the rejection of independent claims 1, 3, and 11 under U.S.C. § 103, prior art references, Uytterhoeven et al. (US 11971740 B2, Fil. Date Jun. 01, 2021, hereinafter Uytterhoeven), How et al. (US 6223313 B1, Pat. Date Apr. 24, 2001, hereinafter How), and Mori (US 2004/0088659 A1, Pub. Date May 6, 2004, hereinafter Mori), as cited by the applicant, fail to disclose or suggest individually or in combination, “a first clock control circuit configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal”, “a second clock control circuit configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal”, and “an enabling circuit configured to provide the first enable signal for the first clock control circuit and provide the second enable signal for the second clock control circuit”, have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, new grounds of rejections are made over Nayak et al. (US 2022/0170982 A1, Pub. Date Jun. 2, 2022, hereinafter Nayak), and applicant’s arguments are rendered moot and not persuasive.
A new ground of rejection is made over Nayak. Therefore, applicant’s arguments are unconvincing and the rejections of independent claims 1, 3, and 11, and their dependent claims, including claims 2, 4-10, and 12, which dependent from and incorporate the limitations of independent claims 1, 3, and 11, are respectively maintained. Rejections based on the newly cited prior art reference follows.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3, 5-6, & 11-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nayak et al. (US 2022/0170982 A1, Pub. Date Jun. 2, 2022, hereinafter Nayak).
Regarding independent claim 1, Nayak, teaches:
A chip (Fig. 1; [0003]-[0004] & [0016]-[0018]: discloses a chip architecture referred to as a multicycle path circuit containing on-chip controllers), comprising:
a first circuit under test (Fig. 1; [0006] & [0017]: discloses a first logic circuit 106 that is tested);
a second circuit under test coupled to the first circuit under test (Fig. 1; [0004] & [0017]: discloses a memory circuit, SRAM 108, coupled to the logic circuit 106 for read/write operations); and
a clock masking circuit comprising (Fig. 1; [0019]-[0024]: discloses a custom on-chip controller 104 that gates and controls clocks to the circuits):
a first clock control circuit configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal (Fig. 1; [0020]-[0021] & [0027]: discloses ICG 118 that receives an initial clock (occ_clk) and an enable signal to output the first clock (logic_clk) to the logic circuit 106);
a second clock control circuit configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal (Fig. 1; [0022]-[0024] & [0027]: discloses ICG 122 that receives the initial clock (occ_clk) and an enable signal to output the second clock (sram_clk) to SRAM 108); and
an enabling circuit configured to provide the first enable signal for the first clock control circuit and provide the second enable signal for the second clock control circuit (Fig. 1; [0005], [0020]-[0022], & [0027]: discloses two pulse shapers that generate specific test clock enable signals (test_clk_enable) for each respective clock path, pulse shaper 200A and pulse shaper 200B);
wherein, during a first operation period, the first enable signal enables the first clock control circuit to provide the first clock signal for the first circuit under test, and the second enable signal disables the second clock control circuit from providing the second clock signal for the second circuit under test (Figs. 4-6; [0027] & [0030]-[0031]: Fig. 5 illustrates a first pulse in at-speed test and timing traces at time 51, where test_clk_enable.logic_clk (first enable) is high and pulses, test_clk_enable.sram_clk (second enable) is low and does not pulse); during a second operation period, the first enable signal disables the first clock control circuit from providing the first clock signal for the first circuit under test, and the second enable signal enables the second clock control circuit to provide the second clock signal for the second circuit under test (Figs. 4-6; [0027] & [0029]-[0030] Fig. 5 illustrates a second pulse in at-speed test and timing traces at time 52, where test_clk_enable.logic_clk (first enable) is low and does not pulse, test_clk_enable.sram_clk (second enable) is high and pulses);
wherein, the first operation period does not overlap with the second operation period (Fig. 5; [0030]-[0031]: figure depicts the pulse at time 51 completed before the pulse at time 52 begins, the enable signals (test_clk_enable) for logic and SRAM are distinct in time/events, showing the enable pulses occurring at distinct, sequential times without overlap).
Regarding independent claim 3, Nayak, teaches:
A chip (Fig. 1; [0003]-[0004] & [0016]-[0018]: discloses a chip architecture referred to as a multicycle path circuit containing on-chip controllers), comprising:
a first circuit under test (Fig. 1; [0006] & [0017]: discloses a first logic circuit 106 that is tested);
a second circuit under test coupled to the first circuit under test (Fig. 1; [0004] & [0017]: discloses a memory circuit, SRAM 108, coupled to the logic circuit 106 for read/write operations); and
a clock masking circuit comprising (Fig. 1; [0019]-[0024]: discloses a custom on-chip controller 104 that gates and controls clocks to the circuits):
a first clock control circuit configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal (Fig. 1; [0020]-[0021] & [0027]: discloses ICG 118 that receives an initial clock (occ_clk) and an enable signal to output the first clock (logic_clk) to the logic circuit 106);
a second clock control circuit configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal (Fig. 1; [0022]-[0024] & [0027]: discloses ICG 122 that receives the initial clock (occ_clk) and an enable signal to output the second clock (sram_clk) to SRAM 108); and
an enabling circuit configured to provide the first enable signal for the first clock control circuit and provide the second enable signal for the second clock control circuit (Fig. 1; [0005], [0020]-[0022], & [0027]: discloses two pulse shapers that generate specific test clock enable signals (test_clk_enable) for each respective clock path, pulse shaper 200A and pulse shaper 200B);
wherein, during a first operation period, the first enable signal enables the first clock control circuit to provide the first clock signal for the first circuit under test, and the second enable signal disables the second clock control circuit from providing the second clock signal for the second circuit under test (Figs. 4-6; [0027] & [0030]-[0031]: Fig. 5 illustrates a first pulse in at-speed test and timing traces at time 51, where test_clk_enable.logic_clk (first enable) is high and pulses, test_clk_enable.sram_clk (second enable) is low and does not pulse); during a second operation period, the first enable signal disables the first clock control circuit from providing the first clock signal for the first circuit under test, and the second enable signal enables the second clock control circuit to provide the second clock signal for the second circuit under test (Figs. 4-6; [0027] & [0029]-[0030] Fig. 5 illustrates a second pulse in at-speed test and timing traces at time 52, where test_clk_enable.logic_clk (first enable) is low and does not pulse, test_clk_enable.sram_clk (second enable) is high and pulses); during a third operation period, the first enable signal enables the first clock control circuit to provide the first clock signal for the first circuit under test, and the second enable signal enables the second clock control circuit to provide the second clock signal for the second circuit under test (Figs. 3-6; [0027]-[0031]: discloses periods where both clocks are active to simulate functional timing, Fig. 5 illustrates logic_clk and sram_clk both pulsing high simultaneously at markers 51 and 52);
wherein, the first operation period, the second operation period, and the third operation period do not overlap with each other (Figs. 3-6; [0019] & [0028]: Figs. 5-6 depict distinct time slots ( 51, 52, 63, 64), pulse shapers allow these to be programmed into distinct non-overlapping periods).
Regarding dependent claim 5, Nayak, teaches:
The chip according to claim 1 (Fig. 1; [0003]-[0004] & [0016]-[0018]), wherein each of the first clock control circuit ([0020]: discloses that the clock control is performed by Integrated clock gaters (ICGs, ICG 118) which are latch-based circuits, comprising a latch and a gating element) and the second clock control circuit is a latch ([0022]-[0024]: ICG 122 constitutes the second clock control circuit latch).
Regarding dependent claim 6, Nayak, teaches:
The chip according to claim 3 (Fig. 1; [0003]-[0004] & [0016]-[0018]), wherein each of the first clock control circuit ([0020]: discloses that the clock control is performed by Integrated clock gaters (ICGs, ICG 118) which are latch-based circuits, comprising a latch and a gating element) and the second clock control circuit is a latch ([0022]-[0024]: ICG 122 constitutes the second clock control circuit latch).
Regarding independent claim 11, Nayak, teaches:
A chip (Fig. 1; [0003]-[0004] & [0016]-[0018]: discloses a chip architecture referred to as a multicycle path circuit containing on-chip controllers), comprising:
a first circuit under test (Fig. 1; [0006] & [0017]: discloses a first logic circuit 106 that is tested);
a second circuit under test coupled to an input end of the first circuit under test (Fig. 1; [0004] & [0017]: discloses a memory circuit, SRAM 108, coupled to the logic circuit 106 for read/write operations);
a clock source circuit configured to provide an initial clock signal ([0018]: discloses an on-chip clock controller OCC 102, providing an initial clock signal, occ_clk); and
a clock masking circuit comprising (Fig. 1; [0019]-[0024]: discloses a custom on-chip controller 104 that gates and controls clocks to the circuits):
a first clock control circuit configured to provide a first clock signal for the first circuit under test according to a first enable signal and the initial clock signal (Fig. 1; [0020]-[0021] & [0027]: discloses ICG 118 that receives an initial clock (occ_clk) and an enable signal to output the first clock (logic_clk) to the logic circuit 106); and
an enabling circuit configured to provide the first enable signal for the first clock control circuit (Fig. 1; [0005] & [0020]-[0022]: discloses a pulse shaper 200A and associated logic (AND 112, Mux 110A) that generate specific test clock enable signals (e.g., test_clk_enable));
wherein, during a first operation period, the first enable signal enables the first clock control circuit to provide the first clock signal for the first circuit under test, and the clock source circuit provides the initial clock signal for the second circuit under test (Fig. 5; [0027], [0030]-[0031]: discloses an “At-Speed Test Mode” (first operation period) where both clocks are active); during a second operation period, the first enable signal disables the first clock control circuit from providing the first clock signal for the first circuit under test, and the clock source circuit provides the initial clock signal for the second circuit under test (Figs. 4-6; [0022], [0027], [0029]-[0030]: discloses a “Stuck-At Test Mode” (second operation period) where the logic clock is disabled (first clock logic _clk is disabled), but the sram clock is provided via bypass ICG 122 (driven by occ_clk/initial clock), providing the clock to the second circuit while the first is disabled);
wherein the first operation period does not overlap with the second operation period (Fig. 5; [0029]-[0031]: discloses the “At-Speed Test Mode” and “Stuck-At Test Mode” are distinct modes selected by control signals, figure depicts the pulse at time 51 completed before the pulse at time 52 begins, the enable signals (test_clk_enable) for logic and SRAM are distinct in time/events, showing the enable pulses occurring at distinct, sequential times without overlap).
Regarding dependent claim 12, Nayak, teaches:
The chip according to claim 11 (Fig. 1; [0003]-[0004] & [0016]-[0018]), further comprising:
a third circuit under test coupled to an output end of the first circuit under test (Fig. 1; [0017]: discloses the SRAM 108 (third circuit), coupled to the output of the logic circuit 106 (first circuit));
wherein, during the first operation period and the second operation period, the clock source circuit further provides the initial clock signal for the third circuit under test (Figs. 3-6; [0022], [0027], & [0029]-[0031]: discloses that the clock source OCC 102 provides the clock (occ_clk which drives sram_clk) used to drive the SRAM 108 (third circuit) in both the “At-Speed”, first period, and “Stuck-At”, second period modes to perform capture operations).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 4, & 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over Nayak, in view of Sera (US 2006/0225010 A1, Pub. Date Oct. 5, 2006, hereinafter Sera).
Regarding dependent claim 2, Nayak, teaches:
The chip according to claim 1 (Fig. 1; [0003]-[0004] & [0016]-[0018]), wherein the enabling circuit comprises (Fig. 1; [0020]-[0022]: custom OCC 104 constitutes the enabling circuit):
a first enabling unit configured to provide the first enable signal for the first clock control circuit (Fig. 1; [0020]-[0021]: discloses generating a first enable (e.g., logic_clk_en or test_clk_enable) to enable the first clock controller, ICG118); and
Nayak, is silent in regard to:
an inverter configured to invert the first enable signal so as to provide the second enable signal for the second clock control circuit.
However, Sera, further teaches:
an inverter configured to invert the first enable signal so as to provide the second enable signal for the second clock control circuit (Fig. 5; [0009], [0013], [0038]-[0040]: discloses using an inverter to split/invert a signal to provide a second, distinct signal).
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement the enabling circuit of Nayak with the inverter-based separation taught by Sera, to generate the second enable signal as the inverse or complement of the first enable signal to guarantee the non-overlapping operation periods (timing conflicts) by using Sera’s technique to prevent hold and setup timing conflict, arriving at the claimed invention with predictable results (KSR).
Regarding dependent claim 4, Nayak, teaches:
The chip according to claim 3 (Fig. 1; [0003]-[0004] & [0016]-[0018]), wherein the enabling circuit comprises (Fig. 1; [0020]-[0022]):
a first enabling unit configured to provide the first enable signal for the first clock control circuit (Fig. 1; [0020]-[0021]: discloses generating a first enable (e.g., logic_clk_en or test_clk_enable) to enable the first clock controller, ICG118);
Nayak, is silent in regard to:
an inverter configured to invert the first enable signal; and
a second enabling unit configured to provide the second enable signal for the second clock control circuit according to a signal obtained by inverting the first enable signal.
However, Sera, further teaches:
an inverter configured to invert the first enable signal (Fig. 5; [0009], [0013], [0026], & [0037]-[0040]: discloses an inverter, INV11, that inverts the signal (DCLK/First enable signal)); and
a second enabling unit configured to provide the second enable signal for the second clock control circuit according to a signal obtained by inverting the first enable signal (Fig. 5; [0026] & [0040]: discloses a second flip-flop unit FF12 that operates on the inverted signal of the first signal source INV11, to generate the second enable output (second enable signal)).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nayak’s enabling circuit (pulse shaper control logic), to include the inverter and the second enabling unit configuration taught by Sera, the modification would be motivated by the need to ensure the first operation period and the second operation period are non-overlapping and self-aligned, using the inverter to guarantee that the second enable signal is only active when the first is inactive and vice versa, arriving at the claimed invention with predictable results (KSR).
Regarding dependent claim 7, Nayak, teaches:
The chip according to claim 2 (Fig. 1; [0003]-[0004], [0016]-[0018], & [0025]-[0026]: discloses that the enabling circuitry (pulse shaper) utilizes scan-based storage elements (scan flip-flops)),
Nayak, is silent in regard to:
wherein the first enabling unit is a scan flip-flop.
However, Sera, further teaches:
wherein the first enabling unit is a scan flip-flop (Fig. 5; [0026]-[0029]: discloses the enabling unit structure FF31 and also discloses the use of scan flip-flops).
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement Sera’s first enabling unit (Fig. 5; FF13) as a scan flip-flop, like FF31 or Nayak’s shift register 204, to allow it to be loaded or observed during the scan shift phase, that is consistent with the scan-based test architecture in both references, ensuring the flip-flop remains part of the scan chain, allowing for the initialization and observation of the controller state, and arriving at the claimed invention with predictable results (KSR).
Regarding dependent claim 8, Nayak, teaches:
The chip according to claim 4 (Fig. 1; [0003]-[0004], [0016]-[0018], & [0025]-[0026]: discloses that the enabling circuitry (pulse shaper) utilizes scan-based storage elements (scan flip-flops)),
Nayak, is silent in regard to:
wherein the first enabling unit is a scan flip-flop.
However, Sera, further teaches:
wherein the first enabling unit is a scan flip-flop (Fig. 5; [0026]-[0029]: discloses the enabling unit structure FF31 and also discloses the use of scan flip-flops).
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement Sera’s first enabling unit (Fig. 5; FF13) as a scan flip-flop, like FF31 or Nayak’s shift register 204, to allow it to be loaded or observed during the scan shift phase, that is consistent with the scan-based test architecture in both references, ensuring the flip-flop remains part of the scan chain, allowing for the initialization and observation of the controller state, and arriving at the claimed invention with predictable results (KSR).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Nayak, in view of Sera, and in further in view of How et al. (US 6223313 B1, Pat. Date Apr. 24, 2001, hereinafter How).
Regarding dependent claim 9, Nayak, teaches:
The chip according to claim 2 (Fig. 1; [0003]-[0004], [0016]-[0018], & [0025]-[0026]),
Uytterhoeven, in combination with Sera, are silent in regard to:
wherein the inverter is a PMOS inverter, an NMOS inverter, or a CMOS inverter.
However, How, further teaches:
wherein the inverter (Fig. 19; [Col. 9, ll. 1-3]) is a PMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704), an NMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704, n-channel transistor 1706), or a CMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704, n-channel transistor 1706, which is also a standard CMOS configuration).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the inverter disclosed by Sera (incorporated into Nayak) as a CMOS inverter, as taught by How, to attain and implement the generic inverter taught by Sera, using the conventional PMOS, NMOS, or CMOS transistor technology of How, where implementing a basic logic element like an inverter using CMOS technology is a fundamental and well-established practice in integrated circuit design, where the CMOS inverter is built from PMOS and NMOS transistors, and selecting from CMOS, PMOS, or NMOS technology to build Sera’s inverter (incorporated into Nayak), would have been an obvious design choice, that would yield predictable results of known test techniques to achieve the claimed elements, to allow for improved fault isolation and test control (KSR).
Regarding dependent claim 10, Nayak, teaches:
The chip according to claim 4 (Fig. 1; [0003]-[0004], [0016]-[0018], & [0025]-[0026]),
Uytterhoeven, in combination with Sera, are silent in regard to:
wherein the inverter is a PMOS inverter, an NMOS inverter, or a CMOS inverter.
However, How, further teaches:
wherein the inverter (Fig. 19; [Col. 9, ll. 1-3]) is a PMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704), an NMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704, n-channel transistor 1706), or a CMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704, n-channel transistor 1706, which is also a standard CMOS configuration).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the inverter disclosed by Sera (incorporated into Nayak) as a CMOS inverter, as taught by How, to attain and implement the generic inverter taught by Sera, using the conventional PMOS, NMOS, or CMOS transistor technology of How, where implementing a basic logic element like an inverter using CMOS technology is a fundamental and well-established practice in integrated circuit design, where the CMOS inverter is built from PMOS and NMOS transistors, and selecting from CMOS, PMOS, or NMOS technology to build Sera’s inverter (incorporated into Nayak), would have been an obvious design choice, that would yield predictable results of known test techniques to achieve the claimed elements, to allow for improved fault isolation and test control (KSR).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kashiwagi (US7222276B2) discloses a scan test circuit including a path for capturing a control signal during a control test mode. Son et al. (US8578227B2) discloses a test device for a system-on-chip that includes a sequential logic circuit and a test circuit. Oruganti et al. (US11689203B1) discloses a method and apparatus for symmetric aging of clock trees. Wu et al. (US10778202B1) discloses a clock switching apparatus and method. Chang (US11740651B2) discloses a clock multiplexer device that includes a first and second control circuitries and an output circuitry and clock switching method. How et al. (US20020073369A1) discloses a method and apparatus for controlling and observing data in a logic block-based ASIC, with a system for testing an integrated circuit, and particularly a gate array with predesigned logic that enables testing of the user-designed circuit. Yu (US20210184657A1) discloses an apparatus for asynchronous latch with improved performance and associated methods. Song (CN114417760B) discloses a trigger unit comprising clock gating circuit. Takemae et al. (US6009039A) discloses a semiconductor device that includes a one-shot pulse generating circuit that generates a one-shot pulse having a predetermined pulse with at a rise or fall timing of a first clock signal. Hsieh (US20230037496A1) disclose a current load circuit and chip for testing a power supply circuit includes a control circuit and a load generation circuit.
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/HUGO NAVARRO/Examiner, Art Unit 2858 01/12/2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 1/15/2026