Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on November 29, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
The Amendment filed April 17, 2026 has been entered. Claims 1, 3, & 5-12 remain pending in the application. Claims 1, 3, & 7-11 have been amended. Claims 2 and 4 have been canceled. Claim 1 has been amended to include the limitations of now canceled claim 2. Claim 3 has been amended to include the limitations of now canceled claim 4. Claims 7 & 9 are amended to depend from claim 1. Claims 8 & 10 are amended to dependent from claim 3. Claim 11 has been amended to include similar limitations of canceled claims 2 & 4.
Response to Arguments
Applicant's arguments filed April 17, 2026, please refer to Applicant’s remarks pp. 6-10, have been entered and fully considered. In light of the amendments, the Applicant has presented a set of arguments pointing out their rationale of how the prior art reference(s) made of record in the most recent Non-Final Office Action, mailed January 20, 2026, does not teach, suggest, and/or disclose the currently recited claim limitations. Applicant’s arguments have been fully considered but they are not persuasive.
Applicant in their submitted response presents the argument that the prior art reference(s), Nayak US2022/0170982, Nayak in view of Sera US2006/0225010, and Nayak in view of Sera, and further in view of How US 6223313, do not teach the limitation of “wherein the enabling circuit comprises: a first enabling unit configured to provide the first enable signal for the first clock control circuit; and an inverter configured to invert the first enable signal so as to provide the second enable signal for the second clock control circuit”, recited in amended independent claim 1, similarly in amended independent claim 3, “wherein the enabling circuit comprises: a first enabling unit configured to provide the first enable signal for the first clock control circuit; an inverter configured to invert the first enable signal; and a second enabling unit configured to provide the second enable signal for the second clock control circuit according to a signal obtained by inverting the first enable signal”, and similarly in amended independent claim 11, “wherein the enabling circuit comprises a first enabling unit and an inverter, the first enabling unit is configured to provide the first enable signal for the first clock control circuit and the inverter is coupled to an output end of the first enabling unit and an input end of the first enabling unit”, all with similar amended claim language limitations. The Applicant provides their rationale on pp. 6-10 of the submitted responses, stating that “If the inverter arrangement of Sera were forcibly incorporated into Nayak as proposed in the Office Action, the two enable signals of Nayak would be locked into a strictly inverse relationship, i.e., a fixed 180-degree phase relationship…”.
The Examiner respectfully disagrees and would like to break the argument presented into two sections. The first part the Examiner would like to highlight is the remarks directed to generalizations not tied to the facts of the application, as to why either the findings of fact or the legal conclusion of obviousness in the rejection is allegedly in error, please refer to MPEP 2143.02 and MPEP 2145(X). As to making a prima facie case of obviousness, upon review, the examiner's rejection satisfied the requirements for applying Rationale B in 2143(I)(B). Furthermore, the rejection can also further apply Rationales E and G in 2143(I)(E) and 2143(I)(G). Please also refer to MPEP 2143(III), In re Keller, 642 F.2d 413, 425, 208 USPQ 871, 881 (CCPA 1981), which states “The test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference…Rather, the test is what the combined teachings of those references would have suggested to those of ordinary skill in the art.”
The second part the Examiner would like to highlight is how the prior art reference(s), Nayak, in view of Sera, read(s) on amended independent claims 1, 3, & 11. Nayak uses two separate parallel pulse shapers (200A and 200B) to generate its two enable signals independently ([0021]-[0022]). Sera teaches the concept of using a scan test clock signal separating circuit that utilizes an inverter (INV11) to invert an incoming signal to generate mutually exclusive, non-overlapping signal for downstream test flip-flops. Sera, further demonstrates, that using the inverter ensures that a high level signal is inverted to a low level, structurally separating the clock components to conduct precise delay testing without overlapping errors. A POSITA would find it obvious to modify Nayak’s dual-pulse-shaper enabling circuit by replacing the second independent pulse shaper (200B) with an inverter connected to the output of the first pulse shaper, to generate the second enable signal from the first signal, as taught by Sera. The motivation would be to reduce hardware overhead/chip area (saving gates required for a second counter/shift register), simplify the test control logic by reducing the number of required pulse shapers, and to guarantee that the two enable signals never overlap (i.e., when one is enabled, the other must be disabled, and vice versa). Therefore, the combination of known elements to yield predictable results, using a known inversion technique to enforce non-overlapping test clocks, would be obvious. Further, replacing the Nayak’s pulse shapers with a single signal generator and inverter to ensure two downstream components operate in mutually exclusive, non-overlapping signals is a textbook design choice that can be modified.
Based on the reasoning provided above, the Examiner believes that Nayak in view of Sera, teach the limitations recited in the claims as currently presented. Therefore, rejection of amended independent claims 1, 3, & 11, and original and amended dependent claims 5-10 & 12, which depend from and incorporate the limitations of amended independent claims 1, 3, & 11, are respectively maintained.
Applicant in their submitted response presents the argument that the prior art reference(s), Nayak US2022/0170982, Nayak in view of Sera US2006/0225010, and Nayak in view of Sera, and further in view of How US 6223313, do not teach the limitation of “wherein the enabling circuit comprises a first enabling unit and an inverter, the first enabling unit is configured to provide the first enable signal for the first clock control circuit and the inverter is coupled to an output end of the first enabling unit and an input end of the first enabling unit”, recited in amended independent claim 11. The Applicant provides their rationale on pp. 6-10 of the submitted responses, stating that “If the inverter arrangement of Sera were forcibly incorporated into Nayak as proposed in the Office Action, the two enable signals of Nayak would be locked into a strictly inverse relationship, i.e., a fixed 180-degree phase relationship…”.
In light of the amendments in independent claim 11, new ground(s) of rejection(s) is/are made over Nayak, in view of Sera, and further in view of Nadeau-Dostie (US6442722). The examiner respectfully disagrees with the Applicant’s contentions that Nayak, in view of Sera, and now in light of new prior art reference(s) Nadeau-Dostie, fail to disclose, teach, and/or suggest individually or in combination, the limitation(s), for the above stated amendment in independent claim 11. Nayak, in view of Sera, and further in view of Nadeau-Dostie, further disclose the additional limitations that have been amended and included in independent claim 11, and meet these requirements. Therefore, the Applicant’s arguments are unconvincing and the rejections of amended independent claim 11, and dependent claim 12, which depends from and incorporates the limitations of amended independent claim 11, are respectively maintained. Rejections based on the newly cited prior art reference(s) follow.
Claim Objections
Applicant is advised that should claims 5, 7, & 9 be found allowable, claims 6, 8, & 10 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, & 5-8 are rejected under 35 U.S.C. 103 as being unpatentable over Nayak et al. (US 2022/0170982 A1, Pub. Date Jun. 2, 2022, hereinafter, Nayak), in view of Sera (US 2006/0225010 A1, Pub. Date Oct. 5, 2006, hereinafter, Sera).
Regarding independent claim 1, Nayak, teaches:
A chip (Fig. 1; [Abstract], [0003]-[0004], & [0015]-[0018]: discloses a chip architecture referred to as a multicycle path circuit containing on-chip controllers), comprising:
a first circuit under test (Fig. 1; [0006] & [0017]: discloses a first logic circuit 106 that is tested);
a second circuit under test coupled to the first circuit under test (Fig. 1; [0004], [0017], & [0019]: discloses a memory circuit, SRAM 108, coupled to the logic circuit 106 for read/write operations); and
a clock masking circuit comprising (Fig. 1; [0019]-[0024]: discloses a custom on-chip controller 104 that gates and controls clocks to the circuits):
a first clock control circuit configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal (Fig. 1; [0020]-[0022] & [0027]: discloses ICG 118 that receives an initial clock (occ_clk) and an enable signal to output the first clock (logic_clk) to the logic circuit 106);
a second clock control circuit configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal (Fig. 1; [0022]-[0024] & [0027]: discloses ICG 122 that receives the initial clock (occ_clk) and an enable signal to output the second clock (sram_clk) to SRAM 108); and
an enabling circuit configured to provide the first enable signal for the first clock control circuit and provide the second enable signal for the second clock control circuit (Fig. 1; [0005], [0020]-[0022], & [0027]: discloses two pulse shapers that generate specific test clock enable signals (test_clk_enable) for each respective clock path, pulse shaper 200A and pulse shaper 200B);
wherein, during a first operation period, the first enable signal enables the first clock control circuit to provide the first clock signal for the first circuit under test, and the second enable signal disables the second clock control circuit from providing the second clock signal for the second circuit under test (Figs. 4-6; [0027] & [0030]-[0031]: Fig. 5 illustrates a first pulse in at-speed test and timing traces at time 51, where test_clk_enable.logic_clk (first enable) is high and pulses, test_clk_enable.sram_clk (second enable) is low and does not pulse); during a second operation period, the first enable signal disables the first clock control circuit from providing the first clock signal for the first circuit under test, and the second enable signal enables the second clock control circuit to provide the second clock signal for the second circuit under test (Figs. 4-6; [0027] & [0029]-[0030]: Fig. 5 illustrates a second pulse in at-speed test and timing traces at time 52, where test_clk_enable.logic_clk (first enable) is low and does not pulse, test_clk_enable.sram_clk (second enable) is high and pulses);
wherein, the first operation period does not overlap with the second operation period (Fig. 5; [0019] & [0028]-[0031]: figure depicts the pulse at time 51 completed before the pulse at time 52 begins, the enable signals (test_clk_enable) for logic and SRAM are distinct in time/events, showing the enable pulses occurring at distinct, sequential times without overlap);
wherein the enabling circuit comprises (Fig. 1; [0005], [0020]-[0022], & [0027]: custom OCC 104 constitutes the enabling circuit):
a first enabling unit configured to provide the first enable signal for the first clock control circuit (Fig. 1; [0020]-[0021]: discloses generating a first enable (e.g., logic_clk_en or test_clk_enable) to enable the first clock controller, ICG118); and
Nayak, is silent in regard to:
an inverter configured to invert the first enable signal so as to provide the second enable signal for the second clock control circuit.
However, Sera, further teaches:
an inverter configured to invert the first enable signal so as to provide the second enable signal for the second clock control circuit (Fig. 5; [0009], [0013], & [0037]-[0040]: discloses using an inverter to split/invert a signal to provide a second, distinct signal and prevent overlap).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the enabling the enabling circuit of Nayak to incorporate an inverter to generate the second enable signal from the first enable signal as the inverse or complement of the first enable signal, as taught by Sera, according to known methods. The motivation for this modification would be hardware optimization and timing assurance. Hardware optimization would reduce the chip area and gate count overhead by eliminating the redundant second enabling unit (pulse shaper 200B and its associated internal counters/shift registers). Timing assurance would guarantee that the first and second enable signals are out of phase and mutually exclusive, therefore, preventing setup and hold timing conflicts (non-overlapping operation periods) due to clock divergence. This constitutes a combination of known elements yielding predictable results (KSR), using a known inversion technique to enforce non-overlapping test clocks.
Regarding independent claim 3, Nayak, teaches:
A chip (Fig. 1; [Abstract], [0003]-[0004] & [0015]-[0018]: discloses a chip architecture referred to as a multicycle path circuit containing on-chip controllers), comprising:
a first circuit under test (Fig. 1; [0006] & [0017]: discloses a first logic circuit 106 that is tested);
a second circuit under test coupled to the first circuit under test (Fig. 1; [0004], [0017], & [0019]: discloses a memory circuit, SRAM 108, coupled to the logic circuit 106 for read/write operations); and
a clock masking circuit comprising (Fig. 1; [0019]-[0024]: discloses a custom on-chip controller 104 that gates and controls clocks to the circuits):
a first clock control circuit configured to provide a first clock signal for the first circuit under test according to a first enable signal and an initial clock signal (Fig. 1; [0020]-[0022] & [0027]: discloses ICG 118 that receives an initial clock (occ_clk) and an enable signal to output the first clock (logic_clk) to the logic circuit 106);
a second clock control circuit configured to provide a second clock signal for the second circuit under test according to a second enable signal and the initial clock signal (Fig. 1; [0022]-[0024] & [0027]: discloses ICG 122 that receives the initial clock (occ_clk) and an enable signal to output the second clock (sram_clk) to SRAM 108); and
an enabling circuit configured to provide the first enable signal for the first clock control circuit and provide the second enable signal for the second clock control circuit (Fig. 1; [0005], [0020]-[0022], & [0027]: discloses two pulse shapers that generate specific test clock enable signals (test_clk_enable) for each respective clock path, pulse shaper 200A and pulse shaper 200B);
wherein, during a first operation period, the first enable signal enables the first clock control circuit to provide the first clock signal for the first circuit under test, and the second enable signal disables the second clock control circuit from providing the second clock signal for the second circuit under test (Figs. 4-6; [0027] & [0030]-[0031]: Fig. 5 illustrates a first pulse in at-speed test and timing traces at time 51, where test_clk_enable.logic_clk (first enable) is high and pulses, test_clk_enable.sram_clk (second enable) is low and does not pulse. The first enable signal enables the first clock control circuit to provide the first clock signal, while the second enable signal disables the second control circuit from providing the second clock signal.); during a second operation period, the first enable signal disables the first clock control circuit from providing the first clock signal for the first circuit under test, and the second enable signal enables the second clock control circuit to provide the second clock signal for the second circuit under test (Figs. 4-6; [0027] & [0029]-[0030]: Fig. 5 illustrates a second pulse in at-speed test and timing traces at time 52, where test_clk_enable.logic_clk (first enable) is low and does not pulse, test_clk_enable.sram_clk (second enable) is high and pulses. The first enable signal disables the first clock control circuit, while the second enable signal enables the second control circuit to provide the second clock signal); during a third operation period, the first enable signal enables the first clock control circuit to provide the first clock signal for the first circuit under test, and the second enable signal enables the second clock control circuit to provide the second clock signal for the second circuit under test (Figs. 3-6; [0027]-[0031]: discloses periods where both clocks are active to simulate functional timing, Fig. 5 illustrates before time (51), both logic_clk and sram_clk, both pulsing high together simultaneously during the scan shift operation, requiring both control circuits to be enabled);
wherein, the first operation period, the second operation period, and the third operation period do not overlap with each other (Figs. 3-6; [0019] & [0028]-[0031]: Figs. 5-6 depict distinct time slots ( 51, 52, 63, 64), pulse shapers allow these to be programmed into distinct non-overlapping periods. Fig. 5 further illustrates that the first operation, the second operation, and the third operation periods occur sequentially and do not overlap with each other).
wherein the enabling circuit comprises (Fig. 1; [0005], [0020]-[0022], & [0027]: custom OCC 104 constitutes the enabling circuit):
a first enabling unit configured to provide the first enable signal for the first clock control circuit (Fig. 1; [0020]-[0021]: discloses generating a first enable (e.g., logic_clk_en or test_clk_enable) to enable the first clock controller, ICG118);
Nayak, is silent in regard to:
an inverter configured to invert the first enable signal; and
a second enabling unit configured to provide the second enable signal for the second clock control circuit according to a signal obtained by inverting the first enable signal.
However, Sera, further teaches:
an inverter configured to invert the first enable signal (Fig. 5; [0009], [0013], [0026], & [0037]-[0040]: discloses an inverter, INV11, that inverts the signal (DCLK/First enable signal)); and
a second enabling unit configured to provide the second enable signal for the second clock control circuit according to a signal obtained by inverting the first enable signal (Fig. 5; [0026] & [0037]-[0040]: discloses a second flip-flop unit FF12 that operates on the inverted signal of the first signal source INV11, to generate the second enable output (second enable signal). Teaches structural separation to prevent overlap: “…the clock signal separating circuit has an inverter INV!!...inverts the signal sent to the H01 terminal…” sending the inverted signal to FF12 (acting as the second enabling unit) to create mutually exclusive outputs, while still allowing a mode (Shift Mode 1) where both final outputs act simultaneously).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify Nayak’s enabling circuit (pulse shaper control logic), to incorporate an inverter to invert the first enabling signal to drive the second enabling unit, as taught by Sera, according to known methods. The motivation for this modification would be hardware efficiency and a structural guarantee of non-overlap. Hardware efficiency would reduce the chip area footprint and overall gate count by eliminating redundant generation of the enable signal (e.g., removing the redundant internal shift register and counter of Nayak’s second pulse shaper) and instead deriving the second signal directly from the first. The structural guarantee of non-overlap would physically ensure that the enable signals for the first and second circuits are mutually exclusive during the testing phases (first and second operation periods), eliminating the setup and hold timing conflicts due to clock divergences, using the inverter to guarantee that the second enable signal is only active when the first is inactive and vice versa. Sera teaches an enabling and separation circuit (10) comprising an inverter (INV11) configured to invert an incoming signal, wherein the inverted signal is fed to a second enabling unit (flip-flop FF12) configured to provide a second output signal according to the inverted first signal. This structural arrangement creates mutually exclusive signals for test operations to guarantee non-overlap, while supporting a shift mode (Shift Mode 1) where downstream circuits can be operated simultaneously. This constitutes and relies on the predictable use of prior art elements (an inverter and sequential flip-flop logic) according to their established functions to achieve the predictable result (KSR) of generating mutually exclusive test clocks.
Regarding dependent claims 5 & 6, Nayak, teaches:
The chip according to claims 1 & 3 (Fig. 1; [Abstract], [0003]-[0004], & [0015]-[0018]), wherein each of the first clock control circuit ([0020]: discloses that the clock control is performed by Integrated clock gates (ICGs, ICG 118) which are latch-based circuits, comprising a latch and a gating element) and the second clock control circuit is a latch ([0022]-[0024]: ICG 122 constitutes the second clock control circuit latch).
Regarding dependent claims 7 & 8, Nayak, teaches:
The chip according to claims 1 & 3 (Fig. 1; [Abstract], [0003]-[0004], [0015]-[0018], & [0025]-[0026]: discloses that the enabling circuitry (pulse shaper) utilizes scan-based storage elements (scan flip-flops)),
Nayak, is silent in regard to:
wherein the first enabling unit is a scan flip-flop.
However, Sera, further teaches:
wherein the first enabling unit is a scan flip-flop (Fig. 5; [0026]-[0029]: discloses the enabling unit structure FF31 and also discloses the use of scan flip-flops).
It would have been obvious to one of ordinary skill in the art before the effective filing date to implement Sera’s first enabling unit (Fig. 5; FF13) as a scan flip-flop, like FF31 or Nayak’s shift register 204, according to known methods. To allow it to be loaded or observed during the scan shift phase, that is consistent with the scan-based test architecture in both references, ensuring the flip-flop remains part of the scan chain. Allowing for the initialization and observation of the controller state, and yield expected predictable results (KSR).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Nayak, in view of Sera, and in further in view of How et al. (US 6223313 B1, Pat. Date Apr. 24, 2001, hereinafter How).
Regarding dependent claims 9 & 10, Nayak, teaches:
The chip according to claims 1 & 3 (Fig. 1; [0003]-[0004], [0016]-[0018], & [0025]-[0026]),
Nayak, in combination with Sera, are silent in regard to:
wherein the inverter is a PMOS inverter, an NMOS inverter, or a CMOS inverter.
However, How, further teaches:
wherein the inverter (Fig. 19; [Col. 9, ll. 1-3]) is a PMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704), an NMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704, n-channel transistor 1706), or a CMOS inverter (Fig. 20; [Col. 20, ll. 49-53]: discloses implementing logic gates with specific transistor configurations, a tri-state buffer 1602 is shown implemented with a p-channel transistor 1704, n-channel transistor 1706, which is also a standard CMOS configuration).
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It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement the inverter disclosed by Sera (incorporated into Nayak) as a CMOS inverter, as taught by How, according to known methods. To attain and implement the generic inverter taught by Sera, using the conventional PMOS, NMOS, or CMOS transistor technology of How. Implementing a basic logic element like an inverter using CMOS technology is a fundamental and well-established practice in integrated circuit design, where the CMOS inverter is built from PMOS and NMOS transistors, and selecting from CMOS, PMOS, or NMOS technology to build Sera’s inverter (incorporated into Nayak), would have been an obvious design choice, that would yield predictable results of known test techniques to achieve the claimed elements, to allow for improved fault isolation and test control (KSR).
Claims 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Nayak, in view of Sera, and further in view of Nadeau-Dostie et al. (US 6442722 B1, Pat. Date Aug. 27, 2002, hereinafter, Nadeau).
Regarding independent claim 11, Nayak, teaches:
A chip (Fig. 1; [Abstract], [0003]-[0004] & [0015]-[0018]: discloses a chip architecture referred to as a multicycle path circuit containing on-chip controllers), comprising:
a first circuit under test (Fig. 1; [0006] & [0017]: discloses a first logic circuit 106 that is tested);
a second circuit under test coupled to an input end of the first circuit under test (Fig. 1; [0004], [0017], & [0019]: discloses a memory circuit, SRAM 108, coupled to the logic circuit 106 for read/write operations);
a clock source circuit configured to provide an initial clock signal ([0018]: discloses an on-chip clock controller OCC 102, providing an initial clock signal, occ_clk); and
a clock masking circuit comprising (Fig. 1; [0019]-[0024]: discloses a custom on-chip controller 104 that gates and controls clocks to the circuits):
a first clock control circuit configured to provide a first clock signal for the first circuit under test according to a first enable signal and the initial clock signal (Fig. 1; [0020]-[0022] & [0027]: discloses ICG 118 that receives an initial clock (occ_clk) and an enable signal to output the first clock (logic_clk) to the logic circuit 106); and
an enabling circuit configured to provide the first enable signal for the first clock control circuit (Fig. 1; [0005], [0020]-[0022], & [0027]: discloses a pulse shaper 200A and associated logic (AND 112, Mux 110A) that generate specific test clock enable signals (e.g., test_clk_enable));
wherein, during a first operation period, the first enable signal enables the first clock control circuit to provide the first clock signal for the first circuit under test (Figs. 3 & 5; [0020], [0027], & [0030]-[0031]: discloses an “At-Speed Test Mode” (first operation period) where both clocks are active, at time (51) in Fig. 5 (first operation period), the test enable signal is high to provide a clock pulse to the circuit under test),
during a second operation period, the first enable signal disables the first clock control circuit from providing the first clock signal for the first circuit under test (Figs. 3-6; [0020], [0022], [0027], [0029]-[0030]: discloses a “Stuck-At Test Mode” (second operation period) where the logic clock is disabled (first clock logic _clk is disabled), but the sram clock is provided via bypass ICG 122 (driven by occ_clk/initial clock), providing the clock to the second circuit while the first is disabled, at time (52) in Fig. 5 (second operation period), the enable signal for the previously targeted circuit goes low, disabling the clock),
wherein the first operation period does not overlap with the second operation period (Fig. 5; [0019] & [0028]-[0031]: discloses the “At-Speed Test Mode” and “Stuck-At Test Mode” are distinct modes selected by control signals, figure depicts the pulse at time 51 completed before the pulse at time 52 begins, the enable signals (test_clk_enable) for logic and SRAM are distinct in time/events, showing the enable pulses occurring at distinct, sequential times without overlap);
Nayak, in combination with Sera, are silent in regard to:
and the clock source circuit provides the initial clock signal for the second circuit under test; and the clock source circuit provides the initial clock signal for the second circuit under test;
wherein the enabling circuit comprises a first enabling unit and an inverter, the first enabling unit is configured to provide the first enable signal for the first clock control circuit, and the inverter is coupled to an output end of the first enabling unit and an input end of the first enabling unit.
However, Nayak, in combination with Nadeau, further teach:
and the clock source circuit provides the initial clock signal for the second circuit under test (Nayak: Figs. 3 & 5; [0020], [0027], & [0030]-[0031]: discloses an “At-Speed Test Mode” (first operation period) where both clocks are active; Nadeau: Figs. 1 & 4; [Col. 8, ll. 22-39]: corroborates by supplying an unmasked ClockHS_raw continuously during testing, Fig. 4 shoes ClockHS_raw running continuously and uninterrupted throughout the test sequence); and the clock source circuit provides the initial clock signal for the second circuit under test (Figs. 3-6; [0020], [0022], [0027], [0029]-[0030]: discloses a “Stuck-At Test Mode” (second operation period) where the logic clock is disabled (first clock logic _clk is disabled), but the sram clock is provided via bypass ICG 122 (driven by occ_clk/initial clock), providing the clock to the second circuit while the first is disabled; Nadeau: Figs. 1 & 4; [Col. 8, ll. 22-39]: teaches that the raw clock continues to run even when the derived capture clocks (ClockHS) are suppressed/disabled by the control signals, Fig. 4 shows ClockHS-raw pulsing continuously while ClockHS is suppressed);
It would have been obvious to one of ordinary skill in the art before the effective filing date to configure Nayak’s testing environment to allow the initial clock (occ_clk) to run continuously to the second circuit under test (logic circuit), as taught by Nadeau, according to known methods. In Nayak, the OCC 102 (clock source) generates occ_clk. Nayak’s masking circuit custom OCC 104 has the ability to pass this occ_clk continuously to the logic circuit (second circuit) if the logic_clk_en signal is held high at the multiplexer 110A, bypassing the test pulse shapers for that specific circuit. Nadeau shows that distributing a continuously running, unmasked raw source clock during a testing sequence, while simultaneously masking/pulsing the clock for an adjacent test domain, is a well-known standard technique in the art. Nadeau teaches providing an uninterrupted ClockHS_raw (initial clock) to the testing domains, which serves as the continuous baseline while the actual capture clocks (ClockHS) are selectively enabled and disabled. The motivation for this combination is to maintain the logic circuit’s state, while selectively enabling/disabling the clock to the first circuit to test for multi-cycle path timing violations, yielding expected predictable results (KSR).
However, Nadeau, further teaches:
wherein the enabling circuit (control signal generation circuit 214) comprises a first enabling unit (timing element 222 which acts as the flip-flop outputting the enable signal) and an inverter (inverter 230), the first enabling unit is configured to provide the first enable signal (SEHS) for the first clock control circuit, and the inverter is coupled to an output end of the first enabling unit and an input end of the first enabling unit (Fig. 9; [Col. 15, ll. 11-24]: Fig. 9 illustrates the inverter 230 situated within a feedback loop, signal path travels from the output side of the timing elements, through inverter 230, into the logic gate (OR gate 228), and directly back into the input end (“D” input) of the timing element 222).
It would have been obvious to one of ordinary skill in the art before the effective filing date to modify the multicycle path testing configuration of Nayak to continuously provide the initial clock signal (unmasked) to the second circuit under test (logic circuit) during both operation periods, as taught by Nadeau, according to known methods. The motivation for this modification is state maintenance and system synchronization. Nayak teaches selectively gating the clocks to the logic circuit and the SRAM to avoid setup and hold timing conflicts during testing. Nadeau teaches that during complex scan testing environments, such as those involving varying clock speeds or multi-cycle paths, would benefit by distributing a continuous, unmasked source clock (e.g., ClockHS_raw) to components to maintain their operational state while selectively pulsing the actual capture clocks (e.g., ClockHS) for targeted testing domains. A POSITA would recognize the benefit of configuring Nayak’s custom OCC 104 such that the logic circuit’s clock enable signal (logic_clk_en) is held high to pass the initial clock (occ_clk) continuously. Doing so, as taught by Nadeau’s raw clock distribution, ensures that the logic circuit maintains its internal state and valid data outputs while the SRAM undergoes alternating test pulses defined by the first and second operation periods. This modification involves applying/combining a known testing methodology (providing a continuous raw clock to maintain state, as taught by Nadeau) to a known structural architecture (Nayak’s independent clock gating paths) to achieve the predictable result (KSR) of an isolated testing environment without data loss in the coupled circuit.
Regarding dependent claim 12, Nayak, teaches:
The chip according to claim 11 (Fig. 1; [Abstract], [0003]-[0004], & [0015]-[0018]), further comprising:
a third circuit under test coupled to an output end of the first circuit under test (Fig. 1; [0017]: discloses the SRAM 108 (third circuit), coupled to the output of the logic circuit 106 (first circuit));
wherein, during the first operation period and the second operation period, the clock source circuit further provides the initial clock signal for the third circuit under test (Figs. 3-6; [0022], [0027], & [0028]-[0031]: discloses that the clock source OCC 102 provides the clock (occ_clk which drives sram_clk) used to drive the SRAM 108 (third circuit) in both the “At-Speed”, first period, and “Stuck-At”, second period modes to perform capture operations).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kwak (US2021/0358527A1) discloses semiconductor devices and semiconductor systems and an inverter.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HUGO NAVARRO/Examiner, Art Unit 2858 May 13, 2026
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 5/20/2026
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