DETAILED ACTION
The Amendment filed December 10, 2025 has been entered. Claims 1-40 are pending. Claim 25 has been cancelled. Claims 35-40 have been added. Claims 1, 2, 15 and 26 are independent.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 35-40 are rejected under AIA 35 U.S.C. 103 as being unpatentable over Kumar et al. (US 2019/0042160) in view of Sarin et al. (US 2021/0264243).
Regarding independent claim 1, Kumar et al. teach a circuit, comprising:
a memory array (see e.g., FIG. 1A) including memory cells arranged in a matrix with plural rows and plural columns, each row including a word line connected to the memory cells of the row, each column including a bit line connected to the memory cells of the column, and each memory cell storing a bit of weight data for an in-memory computation operation (e.g., para. 0034: … compute-in-memory …);
a word line drive circuit for each row having an output connected to drive the word line of the row (see e.g., FIG. 3 and accompanying disclosure);
a row controller circuit coupled to the word line drive circuits and configured to simultaneously actuate a plurality of word lines during said in-memory computation operation (see e.g., FIG. 3 and accompanying disclosure, e.g., para. 0037: … multiple rows simultaneously …); and
a column processing circuit including:
a discharge time sensing circuit for each column configured to measure an amount of time taken during said in-memory computation operation to discharge the bit line from a precharge voltage to a threshold voltage and convert that amount of time (see e.g., FIG. 3: 372 and accompanying disclosure, e.g., para. 0090: … to discharge its accumulated voltage …convert the time to discharge …) to an analog voltage level;
analog-to-digital conversion circuitry configured to convert the analog voltage levels signals to digital signals; and
computation circuitry configured to perform digital signal processing calculations on the digital signals and generate a decision output for the in-memory computation operation (FIGS. 3-8 and accompanying disclosure).
Kumar’s the amount of time converted into voltage level does not disclose to an analog voltage level and ADC.
Sarin et al. teach the deficiencies in e.g., figure 1, 108, along with figures 2-4, and accompanying disclosure.
Kumar and Sarin are analogous art because they both are directed to in-memory computation and one of ordinary skill in the art would have had a reasonable expectation of success to modify Kumar with the specified features of Sarin because they are from the same field of endeavor.
It would have been obvious to one of ordinary skill in the art before the effective filing date to apply the teaching of Sarin et al. to the teaching of Kumar et al. such that a memory, as taught by Kumar et al., utilizes an ADC, as taught by Sarin et al., for the purpose of utilizing amount of current flowing in the respective bit-line and output digital level (see Sarin, e.g., paragraph [0024]), thereby enhancing data read operations.
Regarding claim 35, Kumar et al. and Sarin et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach each memory cell comprises a 6T-type static random access memory (SRAM) cell and the bit line is one bit line of a complementary pair of bit lines for the SRAM cells (FIG. 1B and accompanying disclosure).
Regarding claim 36, Kumar et al. and Sarin et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach each memory cell comprises a 6T-type static random access memory (SRAM) cell and the bit line is both bit lines of a complementary pair of bit lines for the SRAM cells (FIG. 1B and accompanying disclosure).
Regarding claim 37, Kumar et al. and Sarin et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach each memory cell comprises an 8T-type static random access memory (SRAM) cell and the bit line is a read bit line for the SRAM cells (FIG. 1C and accompanying disclosure).
Regarding claim 38, Kumar et al. and Sarin et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach the memory cells are non-volatile memory (NVM) cells and the bit line is an NVM cell bit line (see e.g., paras. 0150).
Regarding claim 39, Kumar et al. and Sarin et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach the row controller circuit simultaneously actuates the plurality of word lines in response to feature data for the in-memory computation operation (e.g., para. 0037).
Regarding claim 40, Kumar et al. and Sarin et al., as combined, teach the limitations of claim 1.
Kumar et al. further teach a variable capacitance circuit (e.g., para. 0045: a sampling capacitance) coupled to each bit line; and a control circuit configured to generate a control signal for setting a capacitance of the variable capacitance circuit coupled to each bit line (see e.g., para. 0045).
Allowable Subject Matter
Claims 2-23 and 26-34 are allowed.
Response to Arguments
Applicant’s amendment filed 12/10/2025, with respect to the rejection(s) of claims 1-34 under 35 USC 102 and 103, have been fully considered but are moot in view of the new ground(s) of rejection. Therefore, it is respectfully submitted that the examiner maintains the rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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/SUNG IL CHO/ Primary Examiner, Art Unit 2825