DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group II (i.e., claims 6-13) in the reply filed on April 8th, 2026 is acknowledged. Claims 1-5 and 14-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected group.
Claim Objections
Claim 11 is objected to because of the following informalities: at line 5, change “a first third metallization level metal structure” to --a first metallization level metal structure--. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6-13 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 6 recites the limitation "a first metal material" at line 11 and again at line 15. Is this the same first metal material in both instances? As best understood and for the purposes of examination, at line 15 “a first metal material” should be --the first metal material--. Claim 6 also recites the limitation “a second metal material” at line 12 and again at line 16. Is this the same second metal material in both instances? As best understood and for the purposes of examination, at line 16 “a second metal material” should be --the second metal material--. Claims 7-13 are rejected as the depend from claim 6.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 6-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Amanapu et al. (US 2020/0111736 A1; hereinafter Amanapu).
With respect to claim 6 (and in view of the 112 rejection), Amanapu teaches a semiconductor structure 200 in Figs. 6-11 with Figs. 1-5 teaching overlapping subject matter comprising:
a first inter-level dielectric (ILD) material layer 206 including a first metallization level of metal structures (210, 212) (see Fig. 6 and paragraphs 56);
a second ILD material layer 214 formed atop the first inter-level dielectric material layer 206, the second inter-level dielectric material layer 214 including a second metallization level of metal structures (216, 218) (see Fig. 7-9 and paragraphs 57, 59);
a third ILD material layer 228 formed atop the second inter-level dielectric material layer 214, the third inter-level dielectric material layer 228 including a third metallization level of metal structures (top of 234 flat metal features) (see Figs. 10, 11, and paragraphs 60, 61);
a metal via structure (part of 234 contacting 216) directly interconnecting a third metallization level metal structure (top of 234 flat metal feature) to a top surface of a second metallization level metal structure 216 in said second ILD material layer 214, said metal via structure (part of 234 contacting 216) comprising a top portion of a first metal material (bulk metal material of 234) and a bottom portion of a second metal material (liner material of 232) connecting said top surface of the second metallization level metal structure 216 (see Figs. 5, 7-11 and paragraphs 49, 52, 57, 61; note liner layers 134 and 232 are equivalent and bulk metal of 136 and 234 are equivalent); and
a metal super via (SVIA) structure (part of 234 contacting 212) directly interconnecting a third metallization level metal structure (top of 234 flat metal feature) to a top surface of a first metallization level metal structure 212 in said first ILD material layer 206, said metal SVIA structure (part of 234 contacting 212) comprising a top portion of the first metal material (bulk metal material of 234) and a bottom portion of the second metal material (liner material of 232) connecting said top surface of the first metallization level metal structure 212 (see Figs. 5-11 and paragraphs 49, 52, 56, 57, 61; note liner layer 134 and 232 are equivalent and bulk metal of 136 and 234 are equivalent).
With respect to claim 7, Amanapu teaches the semiconductor structure as claimed in Claim 6, wherein the first metal material (bulk metal material of 234) is copper and the second metal material (liner material of 232) is a metal selected from the group comprising: cobalt, ruthenium, molybdenum or combinations and alloys thereof (see Figs. 5, 11, and paragraphs 49, 52, 57, 61; note liner layer 134 and 232 are equivalent and bulk metal of 136 and 234 are equivalent).
With respect to claim 8, Amanapu teaches the semiconductor structure as claimed in Claim 6, wherein the metal via structure (part of 234 contacting 216) and metal SVIA structure (part of 234 contacting 212) have a straight profile (see Figs. 6-11 and paragraph 61; note straight sidewall of openings 230).
With respect to claim 9, Amanapu teaches the semiconductor structure as claimed in Claim 6, wherein the metal via structure (part of 234 contacting 216) and metal SVIA structure (part of 234 contacting 212) have no chamfered edges (see Figs. 6-11 and paragraph 61; note straight sidewall of openings 230; note 234 contacting 216 and 212 has no chamfered edges).
With respect to claim 10, Amanapu teaches the semiconductor structure as claimed in Claim 6, further comprising: a first dielectric cap layer 208 formed between said first inter-level dielectric material layer 206 and said second inter-level dielectric material layer 214; and a second dielectric cap layer 222 formed between said second inter-level dielectric material layer 214 and said third inter-level dielectric material layer 228 (see Figs. 6-11 and paragraphs 56, 57, 59, 60; note typo numbering cap layer 2018 but shown as 208 in Fig. 6).
With respect to claim 11, Amanapu teaches the semiconductor structure as claimed in Claim 6, wherein a single metal structure of said third metallization level of metal structures (top of 234 flat metal features) comprises: a metal via structure (part of 234 contacting 216) directly interconnected to a top surface of a second metallization level metal structure 216 in said second ILD material layer 214; and a metal super via (SVIA) structure (part of 234 contacting 212) directly interconnected to a top surface of a first metallization level metal structure 212 in said first ILD material layer 206 (see Figs. 6-11 and paragraphs 56, 57, 61).
With respect to claim 12, Amanapu teaches the semiconductor structure as claimed in Claim 6, wherein each third metallization level metal structure (top of 234 flat metal features) and directly interconnected metal via structure (part of 234 contacting 216) is formed using a via first trench last damascene process (see Figs. 6-11 and paragraphs 56, 57, 61). The limitation “is formed using a via first trench last damascene process” is a product-by-process limitation the applicant is advised that, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process (see MPEP 2113). In this case, the cited limitation failed to distinguish the claimed structure from the prior art which teaches the same structure.
With respect to claim 13, Amanapu teaches the semiconductor structure as claimed in Claim 6, wherein each third metallization level metal structure (top of 234 flat metal features) and directly interconnected metal SVIA structure (part of 234 contacting 212) is formed using a via first trench last damascene process (see Figs. 6-11 and paragraphs 56, 57, 61). The limitation “is formed using a via first trench last damascene process” is a product-by-process limitation the applicant is advised that, even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process (see MPEP 2113). In this case, the cited limitation failed to distinguish the claimed structure from the prior art which teaches the same structure.
Citation of Pertinent Prior Art
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure because each reference teaches a semiconductor structure similar to that of the claimed invention: US 20140284813 A1, US 20190332738 A1, and US 10622301 B2.
Inquiry
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JORDAN M KLEIN whose telephone number is (571)270-7544. The examiner can normally be reached 9:00 am - 5:00 pm.
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/J.M.K/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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