DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
IDS
The IDS document(s) filed on November 29, 2923 has been considered. Copies of the PTO-1449 documents are herewith enclosed with this office action.
Specifications
The title is objected to because a more descriptive title is requested.
Claim Objections
As to claim 1, the Examiner suggests “and including diodes, a number of which is the same as a number of the second terminals.”
Claim Rejections – 35 U.S.C. § 112(b)
The following is a quotation of 35 U.S.C. § 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 5-10 are rejected under 35 U.S.C. § 112(b) or pre-AIA 35 U.S.C. § 112, second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant, regards as the invention.
As to claim 5, there is a lack of antecedent basis for “the first conductor”. Parent claim 1 does not recite a first conductor.
Claim Rejections 35 U.S.C. § 102(a)(1)
The following is a quotation of the appropriate paragraphs of 35 U.S.C. § 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 2 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by Araki (U.S. Patent Publication No. 2023/0188074 A1), hereafter “Araki”.
As to claim 1, Araki teaches:
A plurality of power semiconductor elements (21[U]). See Araki, FIG. 1.
A control chip 41 including a plurality of terminals including a first terminal (Hc) and a plurality of second terminals (Hb[U], Hb[V], Hb[W]) and configured to control each of the plurality of power semiconductor elements, using a corresponding one of power supply voltages supplied to a corresponding one of the plurality of second terminals.
A first conductor 65 configured to supply a predetermined control voltage to the first terminal. Id. at FIG. 4.
A plurality of first wirings each connected to a corresponding one of the plurality of second terminals and configured to supply a corresponding one of the power supply voltages to a corresponding one of the plurality of second terminals. Araki teaches respective first wirings connected to each of the plurality of second terminals and configured to supply corresponding power supply voltages, i.e. Vb[U], Vb[V], Vb[W], to a respective second terminal. Id. at FIG. 1.
A semiconductor chip (30[k]) used for bootstrap operation to generate the power supply voltages and including diodes (D[U], D[V], D[W]) a number of which is same as a number of the second terminals. Araki teaches three diodes and three second terminals. Id.
As to claim 2, Araki teaches the semiconductor chip includes: a semiconductor substrate of a first conductivity type forming anode regions of a plurality of the diodes; and a plurality of second semiconductor layers of a second conductivity type forming cathode regions of a plurality of the diodes and formed side by side at a predetermined distance in a front surface layer of the semiconductor substrate. Id. at ¶¶ [0080]-[0089].
Claims Allowable If Rewritten in Independent Form
Claims 3, 4 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
As to claim 3, Araki does not teach the additional structural limitations of the anode and cathode.
Indication of Allowable Subject Matter
Claims 5-10 would be allowable if rewritten or amended to overcome the rejection(s) under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office action.
As to claim 5, Araki does not teach the additional limitations of the first and second semiconductor layers with respect to the anode and cathode regions.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SUBERR CHI whose telephone number is (571)270-3955. The examiner can normally be reached 10am to 6pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SUBERR L CHI/Primary Examiner, Art Unit 2893
Prosecution Insights