DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1a in the reply filed on 05/13/2026 is acknowledged.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5,9,11,14-15 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2012/0187451 A1 to Saito, “Saito”.
Regarding claim 1, Saito discloses a semiconductor structure (specifically FIG. 9 as applied to FIG. 3 or FIG. 4), comprising:
a substrate (10, ¶ [0030]),
a channel layer (15, ¶ [0032]), and
a barrier layer (16, ¶ [0033]) that are sequentially stacked,
wherein the substrate comprises a plurality of spaced P-type semiconductor regions (11, within substrate in FIG. 3 and FIG. 4, regions 11t being spaced apart by space 11c in FIG. 9, ¶ [0080]-[0082]), each P-type semiconductor region (11t) of the plurality of spaced P-type semiconductor regions is in a strip shape (four strips of 11a as pictured), and an extension direction of the P-type semiconductor region (11) is parallel to a channel length direction.
Regarding claim 2, Saito discloses the semiconductor structure according to claim 1, and Saito further discloses wherein a thickness of the P-type semiconductor region (11) is less than a thickness of the substrate (10, as pictured).
Regarding claim 3, Saito discloses the semiconductor structure according to claim 2, and Saito further discloses wherein a position relationship between the P-type semiconductor region (11) and the substrate (10) comprises the following position relationship:
the P-type semiconductor region (11) partially penetrates through the substrate (10), and the lower surface, away from the channel layer, of the P-type semiconductor region (11), and the sidewalls of the P-type semiconductor region (11), are surrounded by the substrate (10, as pictured).
Regarding claim 4, Saito discloses the semiconductor structure according to claim 1, and Saito further discloses wherein along a channel (15) width direction, a width changing manner of the plurality of spaced P-type semiconductor regions (FIG. 9 regions 11t) comprises gradually decreasing (as pictured due to trapezoidal shape, ¶ [0081]).
Regarding claim 5, Saito discloses the semiconductor structure according to claim 1, and Saito further discloses (FIG. 4):
a dielectric layer (31, ¶ [0056]), located on the barrier layer (16);
a source (20, ¶ [0056]), located on the barrier layer (16);
a drain (21, ¶ [0056]), located on the barrier layer (16); and
a gate (30, ¶ [0056]), located on the dielectric layer (31) and between the source (20) and the drain (21).
Regarding claim 9, Saito discloses the semiconductor structure according to claim 5, and Saito further discloses (FIG. 9) wherein a width of the P-type semiconductor region (portions 11t) gradually decreases along a direction from the gate (30) to the drain (21).
Regarding claim 11, Saito discloses the semiconductor structure according to claim 5, and Saito further discloses wherein a material of the dielectric layer (31) comprises silicon nitride (¶ [0056]).
Regarding claim 14, Saito discloses the semiconductor structure according to claim 1, and Saito further discloses wherein a material of the substrate (10) is a semi-insulating SiC (¶ [0030]).
Regarding claim 15, Saito discloses the semiconductor structure according to claim 1, and Saito further discloses wherein a material combination of the channel layer (15) and the barrier layer (16) is GaN/AIGaN (¶ [0032],[0033],[0109]).
Claims 1-3,5,11-12,14-15 are rejected under 35 U.S.C. § 102(a)(1) as being anticipated by US 2021/0126120 A1 to Piedra et al., “Piedra”.
Regarding claim 1, Piedra discloses a semiconductor structure (Figure 7), comprising:
a substrate (702, ¶ [0095]),
a channel layer (712, ¶ [0099],[0100]), and
a barrier layer (714, ¶ [0101]) that are sequentially stacked,
wherein the substrate comprises a plurality of spaced P-type semiconductor regions (704, 706, 708, ¶ [0097]), each P- type semiconductor region of the plurality of spaced P-type semiconductor regions is in a strip shape (as viewed in Figure 7), and an extension direction of the P-type semiconductor region is parallel to a channel length direction (along the axis from source 722 to drain 724).
Regarding claim 2, Piedra discloses the semiconductor structure according to claim 1, and Piedra further discloses wherein a thickness of the P-type semiconductor region (704, 706, 708) is less than a thickness of the substrate (702, as pictured).
Regarding claim 3, Piedra discloses the semiconductor structure according to claim 2, and Piedra further discloses wherein a position relationship between the P-type semiconductor region (704, 706, 708) and the substrate (702) comprises any one of following position relationships:
the P-type semiconductor region (706, 708) is located inside the substrate (702), and an upper surface, close to the channel layer, of the P-type semiconductor region (706, 708), a lower surface, away from the channel layer, of the P-type semiconductor region (706, 708), and sidewalls of the P-type semiconductor region (706, 708), are surrounded by the substrate (702); and
the P-type semiconductor region (704) partially penetrates through the substrate (702), and the lower surface, away from the channel layer, of the P-type semiconductor region (704), and the sidewalls of the P-type semiconductor region (704), are surrounded by the substrate (702).
Regarding claim 5, Piedra discloses the semiconductor structure according to claim 1, and Piedra further discloses (Figure 7):
a dielectric layer (718, ¶ [0102]), located on the barrier layer (714);
a source (722, ¶ [0103]), located on the barrier layer (714);
a drain (724, ¶ [0103]), located on the barrier layer (714); and
a gate (720, ¶ [0102]), located on the dielectric layer (718) and between the source (722) and the drain (724).
Regarding claim 11, Piedra discloses the semiconductor structure according to claim 5, and Piedra further discloses wherein a material of the dielectric layer (718) comprises silicon nitride (¶ [0102]).
Regarding claim 12, Piedra discloses the semiconductor structure according to claim 1, and Piedra further discloses wherein a thickness of the channel layer (712) is less than 1 µm (e.g. “from about 50 nm to about 300 nm” ¶ [0148]).
Regarding claim 14, Piedra discloses the semiconductor structure according to claim 1, and Piedra further discloses wherein a material of the substrate is a semi-insulating SiC (¶ [0032]).
Regarding claim 15, Piedra discloses the semiconductor structure according to claim 1, and Piedra further discloses wherein a material combination of the channel layer (712) and the barrier layer (714) is GaN/AIGaN (¶ [0099]-[0101],[0056],[0071]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. § 103 as being unpatentable over US 2012/0187451 A1 to Saito, “Saito”, in view of US 2017/0373179 A1 to Sriram et al., “Sriram”.
Regarding claim 10, although Saito discloses the semiconductor structure according to claim 5, Saito fails to clearly teach wherein a P-type doped ion concentration of the P-type semiconductor region (11) gradually decreases along a direction from the gate (30) to the drain (21).
Sriram teaches (e.g. FIG. 11) wherein a P-type doped ion concentration of a P-type semiconductor region (660, from 660a to 660b) gradually decreases (¶ [0107]: “In some embodiments, the graded region 660 may be a laterally graded region having a dopant concentration that decreases laterally from the source region 610 to toward the gate contact 612”, due to graded mask 642, ¶ [0109]).
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Saito with a decreasing graded p-type dopant concentration as taught by Sriram in order to adjust and tune the source current through the barrier and the resulting 2DEG (Sriram ¶ [0107]) since tuning the source resistance (FIG. 3, FIG. 4) can be used to optimize towards an ideal source resistance (¶ [0049],[0068]-[0071]) and, for example, reduce unwanted signal frequency mixing (Sriram ¶ [0005]).
Claim 12 is rejected under 35 U.S.C. § 103 as being unpatentable over US 2021/0126120 A1 to Piedra et al., “Piedra”.
Regarding claim 13, although Piedra discloses the semiconductor structure according to claim 12, Piedra fails to clearly teach in “sufficient specificity” for anticipation, MPEP 2131,03, wherein the thickness of the channel layer is less than 100 nm.
However, Piedra teaches wherein a thickness of the channel layer can be “from about 50 nm to about 300 nm” ¶ [0148] which overlaps with the claimed range.
It would have been obvious before the effective filing date of the claimed invention to one having ordinary skill in the art to have formed the device of Piedra with the thickness of the channel layer within the claimed range as suggested by the overlapping range of Piedra since it has been held that in the case where the claimed ranges "overlap or lie inside ranges disclosed by the prior art" a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990), MPEP 2144.05, and since it has been held that “where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955), In re Hoeschele, 406 F.2d 1403, 160 USPQ 809 (CCPA 1969), wherein in the instant case the thickness of the channel layer is determined by and determines the resulting electrical properties such as operating and switching voltages making it a result effective variable, In re Antonie, 559 F.2d 618, 195 USPQ 6 (CCPA 1977), and MPEP 2144.05 Obviousness of Ranges II. OPTIMIZATION OF RANGES A. Optimization Within Prior Art Conditions or Through Routine Experimentation B. Only Result-Effective Variables Can Be Optimized.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC A WARD whose telephone number is (571)270-3406. The examiner can normally be reached M-F 10-6 ET.
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/Eric A. Ward/ Primary Examiner, Art Unit 2891
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