Prosecution Insights
Last updated: July 17, 2026
Application No. 18/522,909

SEMICONDUCTOR DEVICE AND CORRESPONDING METHOD

Non-Final OA §102
Filed
Nov 29, 2023
Priority
Nov 30, 2022 — IT 102022000024699
Examiner
HENRY, CALEB E
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
STMicroelectronics N.V.
OA Round
1 (Non-Final)
87%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allowance Rate
1082 granted / 1248 resolved
+18.7% vs TC avg
Moderate +6% lift
Without
With
+6.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
32 currently pending
Career history
1285
Total Applications
across all art units

Statute-Specific Performance

§101
0.9%
-39.1% vs TC avg
§103
71.9%
+31.9% vs TC avg
§102
22.9%
-17.1% vs TC avg
§112
1.3%
-38.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1248 resolved cases

Office Action

§102
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1-9 and 21-26 in the reply filed on 3/10/2026 is acknowledged. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-2, 4-9, 21-22 and 24-26 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Ziglioli (20170317060) PNG media_image1.png 318 675 media_image1.png Greyscale PNG media_image2.png 438 621 media_image2.png Greyscale PNG media_image3.png 401 671 media_image3.png Greyscale Regarding claim 1, Ziglioli teaches a device, comprising: a semiconductor die (fig. 5B and 6: 300 or 400) having first and second opposed surfaces (please see topmost and bottommost surfaces of 300 or 400 in fig. 5B); first and second electrically conductive patterns (fig. 5B and 6: 230, 500, 510, 520) configured to provide electrical coupling to the semiconductor die (please see fig. 5B and 6), wherein the first and second electrically conductive patterns extend at the first and second opposed surfaces of the at least one semiconductor die, respectively (please see fig. 5B and 6); an electrical component (fig. 6A and 6B: 810 or 820) having a length transverse to the first and second opposed surfaces of the semiconductor die (please see fig. 6A), wherein the electrical component extends between the first and second opposed surfaces of the semiconductor die (please see fig. 6A) and includes opposed electrical contact end terminals (par. 34, 42 and 44 teaches electrodes being on 230, 500, 510, 520) coupled to the first and second electrically conductive patterns at the first and second opposed surfaces of the semiconductor die (please see fig. 6A and par. 50), respectively; wherein the electrical component is electrically coupled to the semiconductor die via the first and second electrically conductive patterns at the first and second opposed surfaces of the semiconductor die (please see fig. 6A and 50). Regarding claim 2, Ziglioli teaches a device of claim 1, wherein the electrical component comprises an elongate component having a major length between the opposed electrical contact end terminals, the electrical component being arranged with the major length transverse to the first and second opposed surfaces of the semiconductor die (please see fig. 6A). Regarding claim 4, Ziglioli teaches a device of claim 1, wherein the electrical component is arranged adjacent a side of the semiconductor die (please see fig. 6A). Regarding claim 5, Ziglioli teaches a device of claim 1, further comprising an electrically conductive formation (fig. 6A: 200) extending between the first and second electrically conductive patterns at the first and second opposed surfaces of the semiconductor die to provide electrical connection therebetween, wherein the electrically conductive formation is preferably arranged adjacent a side of the semiconductor die (please see multiple portions of 200). Regarding claim 6, Ziglioli teaches a device of claim 5, wherein the semiconductor die is located between the electrical component and the electrically conductive formation (please see fig. 6A). Regarding claim 7, Ziglioli teaches a device of claim 1, wherein the electrical component comprises a capacitor (par. 50-53). Regarding claim 8, Ziglioli teaches a device of claim 1, further comprising an encapsulation (600; par. 37) of insulating material encapsulating the semiconductor die as well as the first and second electrically conductive patterns at the first and second opposed surfaces of the semiconductor die, wherein the electrical component is embedded in said encapsulation (par. 37). Regarding claim 9, Ziglioli teaches a device of claim 8, comprising electrically conductive pathways extending through the encapsulation of insulating material towards at least one of the first and second electrically conductive patterns (par. 37). Regarding claim 21, Ziglioli teaches a device, comprising: a semiconductor die (fig. 5B and 6: 300 or 400) having a first surface and a second surface opposed to the first surface ((please see topmost and bottommost surfaces of 300 or 400 in fig. 5B); a first electrically conductive pattern (fig. 5B and 6: 230, 500, 510, 520) electrically coupled to the semiconductor die at the first surface (please see fig. 5B and 6); a second electrically conductive pattern (fig. 6A: 200) electrically coupled to the semiconductor die at the second surface; an electrical component (fig. 6A and 6B: 810 or 820) having a first electrical contact end terminal coupled to the first electrically conductive pattern and having a second electrical contact end terminal coupled to the second electrically conductive pattern (par. 34, 42 and 44 teaches electrodes being on 200, 230, 500, 510, 520); an encapsulation of insulating material encapsulating the semiconductor die (par. 37), the first electrically conductive pattern at the first surface of the semiconductor die, and the second electrically conductive pattern at the second surface of the semiconductor die, wherein the electrical component is embedded in said encapsulation (par. 37 teaches protecting the entire package). Regarding claim 22, Ziglioli teaches a device of claim 21, wherein the electrical component comprises an elongate component having a major length between the first electrical contact end terminal and the second electrical contact end terminal, the electrical component being arranged with the major length transverse to the first and second surfaces of the semiconductor die (please see fig. 6A). Regarding claim 24, Ziglioli teaches a device of claim 21, further comprising an electrically conductive connection extending through the encapsulation to electrically connect the first electrically conductive pattern to the second electrically conductive pattern (please see multiple portions 230, 500, 510, 520). Regarding claim 25, Ziglioli teaches a device of claim 24, wherein the semiconductor die is located between the electrical component and the electrically conductive connection (please see fig. 6A). Regarding claim 26, Ziglioli teaches a device of claim 21, wherein the electrical component comprises a capacitor (par. 50-53). Allowable Subject Matter Claim 3 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claim 23 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALEB E HENRY whose telephone number is (571)270-5370. The examiner can normally be reached Mon-Fri. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /CALEB E HENRY/Primary Examiner, Art Unit 2818
Read full office action

Prosecution Timeline

Nov 29, 2023
Application Filed
May 12, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
87%
Grant Probability
93%
With Interview (+6.1%)
2y 3m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1248 resolved cases by this examiner. Grant probability derived from career allowance rate.

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