DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of device embodiment 1 as shown in figs. 2 and 3 (claims 1-12, 17-19 readable thereon, claims 13-16 is withdrawn) in the reply filed on 5/13/2026 is acknowledged.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 9 and 10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites the limitation “the second surface of the first semiconductor chip” recited at lines 2-3. It is unclear as to what element said limitation is referring to.
Claim 10 recites the limitation “a second surface” at line 2. It is unclear as to whether said limitation is the same or different than the “second surface” as recited at the second from last line of claim 1.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6, 11, and 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan et al. (US PGPub 2013/0154117; hereinafter “Tan”) in view of Ararao et al. (US PGPub 2006/0012022; hereinafter “Ararao”).
Re claim 1: Tan teaches (e.g. fig. 25) a semiconductor device, comprising: a wiring substrate (support substrate 44’’’’; e.g. paragraph 81); a first semiconductor chip (die 46’’’’; e.g. paragraph 81) having a first surface (bottom surface 58’’’’; e.g. paragraph 81) facing the wiring substrate (44’’’’), the first surface (58’’’’) having a groove (recess 108’’’’; e.g. paragraph 81), the groove (108’’’’) extending across the first surface (58’’’’) and dividing the first surface (58’’’’) into a first portion (left portion of 58’’’’ of fig. 25; hereinafter “1P”) and a second portion (right portion of 58’’’’ of fig. 25; hereinafter “2P”); a second semiconductor chip (die 42’’’’; e.g. paragraph 81) on the wiring substrate (44’’’’), the second semiconductor chip (42’’’’) having a portion inside the groove (108’’’’) of the first semiconductor chip (46’’’’); and a third bonding layer (adhesive element 66’’’’; e.g. paragraph 85) between a bottom of the groove (108’’’’) and a second surface (upper surface 72’’’’ of die 42’’’’; e.g. paragraph 85) of the second semiconductor chip (42’’’’).
Tan is silent as to explicitly teaching a first bonding layer between the first portion of the first surface and the wiring substrate; a second bonding layer between the second portion of the first surface and the wiring substrate.
Ararao teaches (e.g. fig. 13A) a first bonding layer (left adhesive 1332 for left portion of die 1331 of fig. 13A; e.g. paragraph 111; hereinafter “1BL”) between the first portion (1P of Tan/left 1331 of Ararao) of the first surface (58’’’’ of Tan/bottom surface of 1330 of Ararao) and the wiring substrate (44’’’’ of Tan/1302 of Ararao); a second bonding layer (right adhesive 1332 for left portion of die 1331 of fig. 13A; e.g. paragraph 111; hereinafter “2BL”) between the second portion of the first surface (58’’’’ of Tan/bottom surface of 1330 of Ararao) and the wiring substrate (44’’’’ of Tan/1302 of Ararao).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the thicker substrate for the first semiconductor chip such that first and second bonding layers are used as taught by Ararao in the device of Tan in order to have the predictable result of improving heat conduction away from the semiconductor dies and improving device lifespan by more efficiently removing heat from the semiconductor chips (see paragraph 111 of Ararao).
Re claim 2: Tan teaches the semiconductor device according to claim 1, further comprising: a sealing resin (encapsulant material 82’’’; e.g. paragraph 79) that covers the first semiconductor chip (46’’’’).
Re claim 3: Tan in view of Ararao teaches the semiconductor device according to claim 1, wherein the first semiconductor chip (46’’’’) is rectangular in plan view (see fig. 26 which shows the rectangular shape of 46’’’’), and the groove (108’’’’ of Tan/recess 1337 of Ararao) extends from one outer edge (left edge of 1330 of Ararao) of the first semiconductor chip (46’’’’ of Tan/1330 of Ararao) to another outer edge (right edge of 1330 of Ararao) of the first semiconductor chip (46’’’’ of Tan/1330 of Ararao).
Re claim 4: Tan teaches the semiconductor device according to claim 1, wherein the third bonding layer (66’’’’) is a die attach film (66’’’’ is an adhesive element such as a die attach adhesive; e.g. paragraph 85).
Re claim 5: Tan teaches the semiconductor device according to claim 1, further comprising: a first substrate electrode (pads on 44’’’’ which connect to conductive bumps 90’’’’; e.g. paragraph 84; hereinafter “1SE”) on the wiring substrate (44’’’’) at a position facing the second semiconductor chip (42’’’’); and a first chip electrode (pads on 46’’’’ which connect to conductive bumps 90’’’’; e.g. paragraph 84; hereinafter “1CE”) on a surface of the second semiconductor chip (46’’’’) facing the wiring substrate (44’’’’), the first chip electrode (1CE) mounted (through 90’’’’) to the first substrate electrode (1SE).
Re claim 6: Tan teaches the semiconductor device according to claim 5, further comprising: a second chip electrode (48b’’’’) on a third surface (80’’’’) of the first semiconductor chip (46’’’’) on a side of the first semiconductor chip (46’’’’) opposite to that of the first surface (58’’’’); and a second substrate electrode (52b’’’’) on the wiring substrate (44’’’’) at a position not facing the first semiconductor chip (42’’’’); and a first bonding wiring (50b’’’’) that connects the second chip electrode (48b’’’’) to the second substrate electrode (52b’’’’).
Re claim 11: Tan in view of Ararao teaches the semiconductor device according to claim 1, wherein the sealing resin (mold compound 1340; e.g. paragraph 112 of Ararao) fills at least a part of the groove (1337 of Ararao).
Re claim 12: Tan in view of Ararao teaches the semiconductor device according to claim 1, wherein the sealing resin (mold compound 1340; e.g. paragraph 112 of Ararao) contacts an outer edge of the third bonding layer (66’’’’ of Tan/1338 of Ararao).
Claim(s) 7-10 and 17-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tan in view of Ararao as applied to claim 6 above, and further in view of Chiu et al. (US PGPub 2018/0008974; hereinafter “Chiu”).
Re claim 7: Tan in view of Ararao teaches substantially the entire device as claimed in claim 6 except explicitly teaching the semiconductor device further comprising: a third semiconductor chip on the third surface of the first semiconductor chip.
Chiu teaches (e.g. fig. 10) a third semiconductor chip (second chip in the die stack 120; e.g. paragraph 39; hereinafter “3SC”) on the third surface (80’’’’ of Tan/upper surface of bottom chip of chip stack 120 of Chiu) of the first semiconductor chip (46’’’’ of Tan/bottom chip of chip stack 120 of Chiu).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the stack of dies as taught by Chiu in the device of Tan in view of Ararao in order to have the predictable result of increasing integration and increasing performance and capacity of the semiconductor device achieved by stacking multiple dies in a given surface of a mounting substrate.
Re claim 8: Tan in view of Ararao and Chiu teaches the semiconductor device according to claim 7, further comprising: a third chip electrode (48b’’’’ of Tan/wirebond bondpad of bottom chip of chip stack 120 of Chiu) on the third surface (80’’’’ of Tan/upper surface of bottom chip of chip stack 120 of Chiu) of the first semiconductor chip (46’’’’ of Tan/bottom chip of chip stack 120 of Chiu); a third substrate electrode (plural 52b’’’’ of Tan/plural 1314 of Ararao/plural 109,136 of Chiu) on the wiring substrate (44’’’’ of Tan/1302 of Ararao/102 of Chiu); and a second bonding wiring (wirebonds 130,131 of Chiu) that connects the third chip electrode (48b’’’’ of Tan/wirebond bondpad of bottom chip of chip stack 120 of Chiu) and the third substrate electrode (plural 52b’’’’ of Tan/plural 1314 of Ararao/plural 109,136 of Chiu).
Re claim 9: Tan in view of Ararao and Chiu teaches the semiconductor device according to claim 8, wherein the second chip electrode (48b’’’’ of Tan) and the third chip electrode (48b’’’’ of Tan/wirebond bondpad of bottom chip of chip stack 120 of Chiu) are near an outer edge of the second surface (80’’’’ of Tan) of the first semiconductor chip (46’’’’ of Tan) and above the groove (108’’’’ of Tan/1337 of Ararao).
Re claim 10: Tan in view of Ararao teaches substantially the entire device as claimed in claim 1 except explicitly teaching the semiconductor device further comprising: a third semiconductor chip provided on a second surface of the first semiconductor chip on a side of the first semiconductor chip opposite to that of the first surface.
Chiu teaches (e.g. fig. 10) a third semiconductor chip (second chip in the die stack 120; e.g. paragraph 39; hereinafter “3SC”) provided on a second surface (80’’’’ of Tan/upper surface of bottom chip of chip stack 120 of Chiu) of the first semiconductor chip (46’’’’ of Tan/bottom chip of chip stack 120 of Chiu) on a side of the first semiconductor chip (46’’’’ of Tan/bottom chip of chip stack 120 of Chiu) opposite to that of the first surface (58’’’’ of Tan/bottom surface of 1330 of Ararao).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the stack of dies as taught by Chiu in the device of Tan in view of Ararao in order to have the predictable result of increasing integration and increasing performance and capacity of the semiconductor device achieved by stacking multiple dies in a given surface of a mounting substrate.
Re claim 17: Tan in view of Ararao teaches substantially the entire device as claimed in claim 1 except explicitly teaching the semiconductor device wherein the first semiconductor chip is a semiconductor memory chip.
Chiu teaches (e.g. figs. 9 and 10) the first semiconductor chip (46’’’’ of Tan/bottom chip of the stack 124 and all chips 124 are memory dies; e.g. paragraph 31 of Chiu) is a semiconductor memory chip (bottom chip of the stack 124 and all chips 124 are memory dies; e.g. paragraph 31).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the stack of memory dies as taught by Chiu in the device of Tan in view of Ararao in order to have the predictable result of using the device of Tan in an application which requires a memory device with expanded memory capacity..
Re claim 18: Tan in view of Ararao and Chiu teaches the semiconductor device according to claim 17, wherein the second semiconductor chip (42’’’’ of Tan/controller die mounted in a cavity below the memory die stack 120; e.g. paragraph 48 of Chiu) is a semiconductor memory controller chip (42’’’’ of Tan/controller die mounted in a cavity below the memory die stack 120; e.g. paragraph 48 of Chiu).
Re claim 19: Tan in view of Ararao teaches substantially the entire device as claimed in claim 1 except explicitly teaching the semiconductor device according to claim 1, wherein the second semiconductor chip is a semiconductor memory controller chip.
Chiu teaches (e.g. figs. 9 and 10) the second semiconductor chip (42’’’’ of Tan/controller die mounted in a cavity below the memory die stack 120; e.g. paragraph 48 of Chiu) is a semiconductor memory controller chip (42’’’’ of Tan/controller die mounted in a cavity below the memory die stack 120; e.g. paragraph 48 of Chiu).
It would have been obvious to one of ordinary skill in the art at the time of effective filing, absent unexpected results, to use the stack of memory dies and memory controller die as taught by Chiu in the device of Tan in view of Ararao in order to have the predictable result of using the device of Tan in an application which requires a memory device with expanded memory capacity.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JESSE Y MIYOSHI whose telephone number is (571)270-1629. The examiner can normally be reached M-F, 8:30AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JESSE Y MIYOSHI/
Primary Examiner, Art Unit 2898
Prosecution Insights