DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-9 in the reply filed on 4/09/2026 is acknowledged. Claims 10-16 have been canceled.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-4 & 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gomez (US Pub no. 2009/0057854 A1) in view of Xiaochun (US Pub no. 2005/019985 A1)
Regarding claim 1, Gomez et al discloses A method, comprising: providing at least one electrically conductive clip(1) having an end that includes: a planar proximal portion (11)and a distal portion(19) projecting distally beyond the planar proximal portion(11) [0041] fig. 2a, wherein the distal portion(19) includes sculpturing[0042]; arranging at least one semiconductor die (3) at a die mounting location(4) of an electrically conductive substrate(lead frame) [0033], the electrically conductive substrate (lead frame )comprising an array of electrically conductive leads(41/42/43); and arranging said at least one electrically conductive clip (1) in a bridge position between the at least one semiconductor die (3)and at least one electrically conductive lead (43)in the array of electrically conductive leads (41/42/43)to provide electrical coupling therebetween[0036]; wherein arranging said at least one electrically conductive clip (1)comprises: contacting the planar proximal portion (11)with the at least one electrically conductive lead(43); and engaging said sculpturing (19) in the position between the at least one semiconductor chip(3) and the at least one electrically conductive lead(43 or 33) in the array of electrically conductive leads(43/42/41)[0036].
Gomez et al fails to teach electrically conductive leads having openings at a the periphery of said electrically conductive substrate; and engaging said sculpturing in said openings to facilitate immobilizing the at least one electrically conductive clip.
Xiaochun et al discloses electrically conductive lead(140) having openings (112)at a the periphery of said electrically conductive substrate (leadframe); and engaging said clip forks (122) in said openings (112)to facilitate immobilizing the at least one electrically conductive clip(102)[0024]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify Gomez et al with the teaching of Xiaochun et al to provide interlock coupling that constraints the x- and y- dimension displacement and ensure consistent x- and y- dimension control over placement of the clip.
Regarding claim 2, Gomez et al discloses wherein providing the at least one
electrically conductive clip(1) further comprises providing said distal portion (19)with a fork
comprising plural prongs distally projecting beyond the proximal portion(11), wherein said sculpturing(15) is provided in the plural prongs[0042] fig. 2a.
Regarding claim 3, Gomez et al discloses wherein providing the at least one electrically conductive clip(1) further comprises providing said end(19) as a downset portion of the electrically conductive clip(1)[0041].
Regarding claim 4, Gomez et al discloses further comprising providing said sculpturing (15)as at least one protrusion from the distal portion (19)of said end of the at least one electrically conductive
clip(1).
Regarding claim 8, Gomez et al discloses further comprising soldering the at
least one electrically conductive clip(1) to the at least one semiconductor chip (3)[0049] Xiaochun et al teaches at least one electrically conductive lead (140)to provide electrical coupling there between, with the at least one electrically conductive clip (102)immobilized in the bridge said bridge like position as a result of the sculpturing (122)in said distal portion engaging said openings(112)[0024].
Claim(s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gomez (US Pub no. 2009/0057854 A1) in view of Xiaochun (US Pub no. 2005/019985 A1) as applied to claim 1 and further in view of Fuergut (US Pub no. 2021/0225798 A1).
Regarding claim 5, Gomez et al as modified by Xiaochun et al discloses all the claim limitations of claim 1 but fails to teach further comprising providing said sculpturing via additive manufacturing.
Fuergut et al discloses an additive process to form a clip structure(33.2)[0057]. It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to modify the invention of Gomez et al as modified by Xiaochun with the teachings of Fuergut et al to achieve sculpturing since a particular additive processing was recognized as part of the ordinary capabilities of one skilled in the art. One of ordinary skill in the art would have been capable of applying this known technique to a known device (method, or product) that was ready for improvement and the results would have been predictable to one of ordinary skill in the art. In re Nilssen, 851 F.2d 1401, 7 USPQ2d 1500 (Fed. Cir. 1988)
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gomez (US Pub no. 2009/0057854 A1) in view of Xiaochun (US Pub no. 2005/019985 A1)as applied to claim 1 and further in view of Kalfus (US Patent 4935803 A)
Regarding claim 9, Gomez et al as modified by Xiaochun et al discloses all the claim limitations of claim 1 but fails to teach including the electrically conductive substrate in a set of electrically conductive substrates having respective die mounting locations, wherein the electrically conductive substrates in the set are coupled via sacrificial connecting bars between electrically conductive leads in adjacent electrically conductive substrates in the set; processing the electrically conductive substrates in the set coupled via the sacrificial connecting bars by arranging semiconductor dice at respective die mounting locations and arranging electrically conductive clips in the bridge a bridge-like position between semiconductor
dice arranged at respective die mounting locations and electrically conductive leads in arrays of electrically conductive leads of the electrically conductive substrates in the set to provide electrical coupling therebetween; and subsequent to said processing, cutting at the sacrificial connecting bars the set of electrically conductive substrates having said semiconductor dice and said electrically conductive clips arranged thereon to produce, as a result of said cutting, singulated semiconductor devices wherein the distal portions of the electrically conductive clips are exposed at a the periphery of the
singulated semiconductor devices.
However, Kalfus et al discloses a method including the electrically conductive substrate (120)in a set of electrically conductive substrates (120D-120E)having respective die mounting locations(13) (col. 7, lines 25-27 & lines 48-49), wherein the electrically conductive substrates(120D-120E)in the set are coupled via sacrificial connecting bars (122/124)between electrically conductive leads (12/50)in adjacent electrically conductive substrates(120D-120E)in the set (fig. 10)(col. 7, lines 47-54); processing the electrically conductive substrates ((120D-120E))in the set coupled via the sacrificial connecting bars(122/124) by arranging semiconductor dice (16)at respective die mounting locations(13) and arranging electrically conductive clips(60) in the bridge a bridge-like position between semiconductor dice (16)arranged at respective die mounting locations(13) and electrically conductive leads(12/50) in arrays of electrically conductive leads(12/50) of the electrically conductive substrates((120D-120E)) in the set to provide electrical coupling therebetween(col. 8 lines 30-34); and subsequent to said processing, cutting at the sacrificial connecting bars(122/124) the set of electrically conductive substrates((120D-120E)) having said semiconductor dice (16)and said electrically conductive clips (60)arranged thereon to produce, as a result of said cutting, singulated semiconductor devices wherein the distal portions of the electrically conductive clips are exposed at a the periphery of the
singulated semiconductor devices(col. 9 lines 15-20). It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to further modify Gomez et al and Xiaochun et al with the teachings of Kalfus et al to provide a fabrication process for power devices.
Allowable Subject Matter
Claim 6-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LATANYA N CRAWFORD EASON whose telephone number is (571)270-3208. The examiner can normally be reached Monday-Friday 8:30 AM-4:30 PM.
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/LATANYA N CRAWFORD EASON/Primary Examiner, Art Unit 2813
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