DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species 1 (claims 1-8, 11-20) in the reply filed on 04/13/2026 is acknowledged.
Claims 9 and 10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected Species 2, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 01/04/2026,
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-6, 11, 12, 14-17 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Jung (US 2022/0238544).
Regarding claim 1, Yun discloses a non-volatile memory device comprising: a memory cell array including a plurality of word lines stacked (Figs.1, 3, WL) on a substrate in a first direction perpendicular to an upper surface of the substrate ([0017]), and a common source line (CSL) below the plurality of word lines (WL1-WL8); a plurality of driving signal lines (SS) connected to a row decoder (Fig.1, numeral 2); and a plurality of pass transistor arrays (3) each including a plurality of vertical pass transistors (fig.3, PTR) respectively connected the plurality of driving signal lines (DSI) and the plurality of word lines (WL), wherein each of the plurality of pass transistor arrays further include an active region including a drain (D) ([0080]) to which at least two of the plurality of vertical pass transistors are simultaneously bonded (Fig.4A), and a main contact applying a signal to the active region ([0008];[0128]; Fig.18).
Regarding claim 2, Yun discloses wherein each of the plurality of vertical pass transistors include: a gate (Fig.10A-C, numeral 520) extending in the first direction; a vertical channel (512) penetrating the gate in the first direction; and a gate insulating film (514) between the vertical channel and the gate (Fig.10C).
Regarding claim 3, Yun discloses wherein the pass transistor array (PTR) further includes a contact respectively connecting the plurality of vertical pass transistors and the plurality of word lines (WL) to each other (Fig.6A).
Regarding claim 4, Yun discloses the active region is parallel to a second direction perpendicular to the first direction, and the gate has a first angle with the second direction (Fig.8A; note: “angle is not defined”).
Regarding claim 5, Yun discloses wherein the plurality of pass transistor arrays (PTR) are on a plane parallel to the substrate parallel to each other (Fig.4A).
Regarding claim 6, Yun discloses wherein the pass transistor array further includes a first vertical pass transistor and a second vertical pass transistor sharing one drain, and the first vertical pass transistor and the second vertical pass transistor are arranged with a first distance therebetween ([0073]).
Regarding claim 11, Yun discloses wherein the pass transistor array has a first angle with a second direction perpendicular to the first direction ([0079]).
Regarding claim 12, Yun discloses wherein the plurality of pass transistor arrays (PTR) are parallel to each other (Fig.4A).
Regarding claim 14, Yun discloses a non-volatile memory device comprising: a memory cell array including a first word line, a second word line stacked on the first word line, a third word line stacked on the second word line, and a fourth word line stacked on the third word line (Fig.3, WL); and first to fourth vertical pass transistors (PRSR1) respectively connected to the first word line to the fourth word line, wherein two or more of the first to fourth vertical pass transistors share one drain of an active region ([0073]).
Regarding claim 15, Yun discloses the first vertical pass transistor and the second vertical pass transistor share a drain of a first active region, and the third vertical pass transistor and the fourth vertical pass transistor share a drain of a second active region ([0101]).
Regarding claim 16, Yun discloses wherein the first active region (100) and the second active region (200) are on a same plane parallel to each other (Fig.4A).
Regarding claim 17, Yun discloses wherein the first active region and the second active region have a same size ([0106]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yun.
Regarding claim 7, Yun does not disclose wherein the pass transistor array further includes first to fourth vertical pass transistors sharing one drain, and the first to fourth vertical pass transistors are arranged with a first distance between each other.
Yun however discloses that two or more pass transistors are coupled in series by sharing a drain ([0073]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have first to fourth vertical pass transistors sharing one drain, and the first to fourth vertical pass transistors are arranged with a first distance between each other for the purpose reducing the area of the entire layout (Yun, [0073]).
Regarding claim 8, Yun does not disclose wherein the first to fourth vertical pass transistors are arranged in a 1*4 form.
Yun however discloses that two or more pass transistors are coupled in series by sharing a drain ([0073]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to the first to fourth vertical pass transistors are arranged in a 1*4 form for the purpose reducing the area of the entire layout (Yun, [0073]).
Regarding claim 18, Yun does not disclose wherein the first to fourth vertical pass transistors share a drain of one active region.
Yun however discloses that two or more pass transistors are coupled in series by sharing a drain ([0073]).
It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to have first to fourth vertical pass transistors sharing one drain, and the first to fourth vertical pass transistors are arranged with a first distance between each other for the purpose reducing the area of the entire layout (Yun, [0073]).
Allowable Subject Matter
Claims 13 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
The following is a statement of reasons for the indication of allowable subject matter:
The search of the prior art does not disclose or reasonably suggest wherein the plurality of vertical pass transistors are on the active region in a radial shape with respect to the main contact as required by claim 13.
The search of the prior art does not disclose or reasonably suggest wherein the first to fourth vertical pass transistors share one main contact as required by claim 19.
The search of the prior art does not disclose or reasonably suggest plurality of vertical pass transistors sharing a drain of an active region and sharing a main contact as required by claim 20.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm.
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/JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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