DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 07-29-2026 have been fully considered but they are not persuasive.
In response to applicant’s argument that the references allegedly fail to show the amended, not previously presented, feature of the invention (i.e., the second power wiring) the argument is found to be unpersuasive.
As for the reference it appears that the reference does teach the amended, not previously presented, feature of the invention. Please see rejection for further mapping and clarification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chanyoungas Park et al. (US 11637151 B2) Hereinafter referred to as “Park” further in view of Yujin Jeon et al. (US 11665937 B2) Hereinafter referred to as “Jeon”.
Regarding Claim 1 Park
A display device (Fig 11 element10), comprising:
a substrate (100) ;
a display area comprising a plurality of pixels (P);
a sensor hole area (through holes R1 and/or R2);
a sensor non-display area (NDA1) disposed between the display area and the sensor hole area (Fig 11);
a first conductive layer (SLa and SLb) disposed on the substrate and comprising a scan wiring (SLa and SLb) connected to the plurality of pixels (P Col. 11 lines 59-67) and extending along a first direction (X-axis);
a second conductive layer (the layer of PLa and PLb); and
a high voltage power wiring (PLa and PLb) connected to the plurality of pixels, wherein:
the high voltage power wiring comprises a hole-surrounding high voltage power wiring (PLa and PLb of PLa and PLb) surrounding the sensor non-display area on a plane (Col. 23 lines 22-24); and
at least a portion of the hole-surrounding high voltage power wiring is disposed in the second conductive layer .(PLa and PLb are of the layer of PLa and PLb); and
the high voltage power wiring further comprises a first high voltage power wiring (PLb) and a second high voltage power wiring (PLa), the first high voltage power wiring extending along a second direction (Y-axis) intersecting the first direction (X-axis), the second high voltage power wiring (PLa) extending in the second direction being electrically connected to the hole-surrounding high voltage power wiring. (PLa surrounds at least a portion of the hole and is electrically connected to itself.)
Though Park does teach PLa and PLb intersecting SLa and SLb in figure 11 park is not relied on to teach that PLa and PLb are disposed on SLa and SLb in the limitation:
a second conductive layer disposed on the first conductive layer;
Jeon explicitly teaches
a second conductive layer (PL and HL) disposed on the first conductive layer (SL);(Col. 11 lines 8-11, 25-27, 31-32 )
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park such that the second conductive layer disposed on the first conductive layer, as described in Jeon because the modification allows for the Reduction of electrostatic discharge damage since HL is above SL we are able to have 113 to insulate most of SL from HL since HL is connected to a metal layer. (Jeon Col. 18-19 lines 66-3, Col 19 lines 20-28)
Regarding Claim 3 Park in view of Jeon teaches
The display device of claim 1,
Park further teaches
wherein the hole-surrounding high voltage power wiring (Fig 11. PLa and PLb) has a larger width than the first high voltage power wiring.(PLa) (the width of PLa and PLb will always be wider than its subset PLa)
Regarding Claim 4 Park in view of Jeon teaches
The display device of claim 1,
Park further teaches
wherein the high voltage power wiring (PLa and PLb) does not overlap the sensor non-display area. (Col. 23 lines 22-24)
Regarding Claim 5 Park in view of Jeon teaches
The display device of claim 1,
Park further teaches
wherein the scan wiring (SLa and SLb) extends along the first direction (x-axis) and by passes the sensor hole area on a plane within the sensor non-display area. (Fig. 11)
Regarding Claim 6 Park in view of Jeon teaches
The display device of claim 1,
Park further teaches
wherein the high voltage power wiring (PLa and PLb) further comprises an 3-1th power wiring portion (see diagram) disposed at an upper side (+Y side) of the hole-surrounding high voltage power wiring on a plane and connected to the hole-surrounding high voltage power wiring, and a 3-2th power wiring portion (see diagram) disposed at a lower side (-Y side) of the hole-surrounding high voltage power wiring on a plane and connected to the (at least partially surrounding) hole-surrounding high voltage power
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wiring.
Regarding Claim 7 Park in view of Jeon teaches
The display device of claim 6,
Park further teaches
wherein the 3-lth power wiring portion and the 3-2th power wiring portion extend along the second direction (Y) intersecting the first direction. (X)
Claim(s) 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Park, and further in view of Gen Li (US 12058905 B2) hereinafter referred to as “Li”.
Regarding Claim 17 Park teaches
A display device (Fig 11 element10), comprising:
a substrate (100);
a display area comprising a plurality of pixels (P);
a hole area (through holes R1 and/or R2);
a non-display area (NDA1) disposed between the display area and the hole area (Fig 11);
a conductive layer (PLa and PLb) disposed on the substrate; and
a power wiring (Driving voltage lines PLa and PLb) connected to the plurality of pixels (P) and configured to provide power,
wherein: at least a portion of the power wiring is disposed in the conductive layer ;(PLa and PLb and disposed in PLa and PLb);
and the power wiring comprises a hole-surrounding power wiring surrounding the non-display area (PLa and PLb of PLa and PLb, Col. 23 lines 22-24);
Park does not explicitly teach
and the hole-surrounding power wiring completely surrounds the non-display area.
Li teaches a power line that does teach
the hole-surrounding power wiring (210 and 211) completely surrounds the non-display area (22) (Fig 1b)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park such that the hole-surrounding power wiring completely surrounds the non-display area, as described in Li because the modification allows for the plurality of first pixel rows to receive the same first voltage since they are connected with the same voltage bus line 210. (Col 7 lines 32-50)
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Friday, 9:00a.m. - 5:00p.m. ET..
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/JAIME LYNN SPRENGER/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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