DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Election/Restrictions
Claims 8-16 and 18-21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 04-02-2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6 and 7 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “upper high voltage power wiring” and “lower high voltage power wiring” in claims 6 and 7 is a relative term which renders the claim indefinite. The term are not defined by the claim, the specification does not provide a standard for ascertaining the requisite degree, and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is unclear what is included in the scope of these terms and examiner is interpreting them as upper and lower portions of the high voltage power wiring for the purposes of examination. An explanation and/or examples from the specification would be greatly appreciated to help examiner search the invention to the greatest capability.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 17 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Chanyoungas Park et al. (US 11637151 B2) Hereinafter referred to as “Park”
Regarding Claim 17 park teaches
A display device(Fig 11 element 10), comprising:
a substrate(100);
a display area comprising a plurality of pixels(P);
a hole area(through holes R1 and/or R2);
a non-display area disposed between the display area and the hole area(NDA1 Fig 11);
a conductive layer disposed on the substrate(PLa and PLb);
and a power wiring (Driving voltage lines PLa and PLb) connected to the plurality of pixels (P) and configured to provide power, wherein:
at least a portion of the power wiring is disposed in the conductive layer;(PLa and PLb and disposed in PLa and PLb)
and the power wiring comprises a hole-surrounding power wiring surrounding the non-display area (PLa and PLb of PLa and PLb, Col. 23 lines 22-24)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chanyoungas Park et al. (US 11637151 B2) Hereinafter referred to as “Park” further in view of Yujin Jeon et al. (US 11665937 B2) Hereinafter referred to as “Jeon”.
Regarding Claim 1 Park teaches
A display device (Fig 11 element10), comprising:
a substrate(100);
a display area comprising a plurality of pixels(P);
a sensor hole area (through holes R1 and/or R2);
a sensor non-display area(NDA1) disposed between the display area and the sensor hole area (Fig 11);
a first conductive layer (SLa and SLb) disposed on the substrate and comprising a scan wiring (SLa and SLb) connected to the plurality of pixels (P Col. 11 lines 59-67) and extending along a first direction (X-axis);
a second conductive layer (the layer of PLa and PLb);
and a high voltage power wiring(PLa and PLb) connected to the plurality of pixels,
wherein:
the high voltage power wiring comprises a hole-surrounding high voltage power wiring (PLa and PLb of PLa and PLb) surrounding the sensor non-display area on a plane (Col. 23 lines 22-24); and
at least a portion of the hole-surrounding high voltage power wiring is disposed in the second conductive layer.(PLa and PLb are of the layer of PLa and PLb)
Though Park does teach PLa and PLb intersecting SLa and SLb in figure 11 park is not relied on to teach that PLa and PLb are disposed on SLa and SLb in the limitation:
a second conductive layer disposed on the first conductive layer;
Jeon explicitly teaches
a second conductive layer (PL and HL) disposed on the first conductive layer (SL);(Col. 11 lines 8-11, 25-27, 31-32 )
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the device of Park such that the second conductive layer disposed on the first conductive layer, as described in Jeon because the modification allows for the Reduction of electrostatic discharge damage since HL is above SL we are able to have 113 to insulate most of SL from HL since HL is connected to a metal layer. (Jeon Col. 18-19 lines 66-3, Col 19 lines 20-28)
Regarding Claim 2 Park in view of Jeon teaches
The display device of claim 1,
Park further teaches
wherein the high voltage power wiring further(PLa and PLb) comprises a first high voltage power wiring(PLa) extending along a second direction (y-axis) intersecting the first direction(x-axis).(Fig11)
Regarding Claim 3 Park in view of Jeon teaches
The display device of claim 2,
Park further teaches
wherein the hole-surrounding high voltage power wiring(Fig 11. PLa and PLb) has a larger width than the first high voltage power wiring.(PLa) (the width of PLa and PLb will always be wider than its subset PLa)
Regarding Claim 4 Park in view of Jeon teaches
The display device of claim 1,
Park further teaches
wherein the high voltage power wiring(PLa and PLb) does not overlap the sensor non-display area. (Col. 23 lines 22-24)
Regarding Claim 5 Park in view of Jeon teaches
The display device of claim 1,
Park further teaches
wherein the scan wiring (SLa and SLb) extends along the first direction (x-axis) and by passes the sensor hole area on a plane within the sensor non-display area. (Fig. 11)
Regarding Claim 6 Park in view of Jeon teaches
The display device of claim 1,
Park further teaches
wherein the high voltage power wiring(PLa and PLb) further comprises an upper high voltage power wiring (upper portion of PLa and PLb) disposed at an upper side of the hole-surrounding high voltage power wiring(disposed at the upper side of PLa and PLb) on a plane and connected to the hole-surrounding high voltage power wiring(connected to PLa and PLb), and a lower high voltage power wiring(lower portion of PLa and PLb) disposed at a lower side of the hole-surrounding high voltage power wiring(disposed at the lower side of PLa and PLb) on a plane and connected to the hole-surrounding high voltage power wiring. (connected to PLa and PLb)
Regarding Claim 7 Park in view of Jeon teaches
The display device of claim 6,
Park further teaches
wherein the upper high voltage power wiring(upper portion of PLa and PLb) and the lower high voltage power wiring(lower portion of PLa and PLb) extend along a second direction (y-axis) intersecting the first direction(x-axis). (Fig 11)
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. LEE; Jinuk (US 20240206260 A1), Jaehee Park (US12219846B2), Yeseul HAN (US12004393B2) (power wiring above scan lines), SONG; Hwayoung (US 20200058728 A1).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAIME LYNN SPRENGER whose telephone number is (571)272-8444. The examiner can normally be reached Monday - Thursday, 7:30a.m. - 5:00p.m. ET..
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at 571-272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAIME LYNN SPRENGER/Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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