DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I, Species 3 (Fig. 2), claims 1-10 and 20-26, in the reply filed on March 27, 2026 is acknowledged. Claims 11-19 and 27-29 have been withdrawn. Action on the merits is as follows:
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-10 and 20-26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yang e al (Yang) (US 2022/0310489 A1) in view of Kim et al (Kim) (US 2022/0157787 A1).
In regards to claim 1, Yang (Fig. 4 and associated text and items) discloses an assembly (Fig. 4) comprising: a reconstituted element (item 400) having a front surface and a back surface, the reconstituted element (item 400) comprising: a semiconductor die (item 400a plus 420 plus 446) having a front side and a back side, the semiconductor die (item 400a plus 420) including circuitry closer to the front side than to the back side and a via (item 441, 411, mentioned as 441 in the specification but item 411 in the drawings) extending from the back side of the semiconductor die (item 400a plus 420) to connect to the circuitry; an insulating material (item 484) disposed along a side surface of the semiconductor die (item 400a); and an interconnect structure (item 422a, 422b) configured to electrically connect the power rail (item 446) to the via (item 441, 411) and to deliver power (paragraph 87, item 441) to the semiconductor die (item 400a plus 420 plus 446) from the back side of the semiconductor die (item 400a plus 420 plus 446), but does not specifically disclose a power rail extending from the front surface to the back surface of the reconstituted element and configured to deliver power to the semiconductor die.
Kim (Figs. 1, 3A, 4A, 4B and associated text) discloses one or more through mold vias (TMVs 305, 405) extending from a connector to an integrated voltage regulator die (item 105) and routing the power (paragraph 37), thus a power rail (items 305, 405) extending from the front surface to the back surface of the reconstituted element and configured to deliver power to the semiconductor die (item 103).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim for the purpose of power distribution.
In regards to claim 2, Yang as modified by Kim does not specifically disclose wherein the insulating material comprises an inorganic dielectric.
In regards to claim 3, Yang as modified by Kim does not specifically disclose wherein the insulating material comprises silicon oxide.
In regards to claim 4, Yang as modified by Kim does not specifically disclose wherein the insulating material comprises an organic dielectric.
In regards to claims 2-4, Yang (paragraph 83, Figs. 3G, 4 and associated text) discloses wherein the insulating material/encapsulant layer (items 384, 484) can be a molding compound, epoxy, or the like (paragraph 83). Examiner notes that is well known in the art that silicon oxide, organic and/or inorganic dielectrics can be used as encapsulants/insulating material/layers.
It would have been obvious to modify the invention to include an insulating material comprising silicon oxide, organic and/or inorganic dielectrics, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 5, Yang (Fig. 4 and associated text and items) discloses wherein the interconnect structure (items 422a, 422b) comprises a redistribution layer (item 478) disposed on the back surface of the reconstituted element (item 400).
In regards to claim 6, Yang (Fig. 4 and associated text and items) discloses wherein the interconnect structure (item 422b) comprises an interconnect element that is hybrid bonded to the back side of the semiconductor die (paragraphs 25, 69).
In regards to claim 7, Yang (Figs. 3, 4 and associated text and items) discloses wherein the interconnect structure (item 322a) comprises one or more metallization layers.
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to combine various embodiments of Yang for the purpose of an electrical connection and package configuration.
In regards to claim 8, Yang (Figs. 3-5 and associated text and items) discloses further comprising a power delivery die (item 500a), wherein the power delivery die (item 500a) is hybrid bonded to the back surface of the reconstituted element.
In regards to claim 9, Yang as modified by Kim (Figs. 1, 3A, 4A, 4B and associated text) discloses wherein the power delivery die (items 105 or 107) comprises a redistribution layer (item 173).
In regards to claim 10, Yang (Figs. 3-5 and associated text and items) as modified by Kim (Figs. 1, 3A, 4A, 4B and associated text) discloses wherein the reconstituted element (item 400, Yang, Figs. 1, 3A, 4A, 4B, Kim) further comprises an integrated voltage regulator (item 105).
In regards to claim 20, Yang (Figs. 3-5 and associated text and items) discloses wherein the circuitry (item 420) comprises one or more transistors (paragraphs 43, 71).
In regards to claim 21, Yang as modified by Kim does not specifically disclose wherein the semiconductor die has a thickness less than 5 μm.
In regards to claim 22, Yang as modified by Kim does not specifically disclose wherein the semiconductor die has a thickness less than 1 μm.
It would have been obvious to one having ordinary skill in the art at the time of the invention to modify the invention to include a semiconductor die having a thickness less than 5 μm or less than 1 μm for the purpose of package size, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art (In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980)).
In regards to claim 23, Yang (Figs. 3-5 and associated text and items) discloses wherein the semiconductor die (item 100a-100c, 400a) is a logic die or a processor die (paragraph 35).
In regards to claim 24, Yang (Figs. 3, 4 and associated text and items) discloses an assembly comprising: an insulating material (item 384, 484); an integrated device die (items 100a-100c, 400a) at least partially embedded in the insulating material (item 384, 484), the integrated device die (items 100a-100c, 400a) having a front side and a back side, the integrated device die (items 100a-100c, 400a) including circuitry (item 420) closer to the front side than to the back side and a power delivery structure (items 441, 411) extending from the back side of the integrated device die (items 100a-100c, 400a) to connect to the circuitry (item 420); and an interconnect structure (items 322a, 422a, 422b) over the insulating material (items 384, 484), but does not specifically disclose a power rail extending through the insulating material…the power rail, and the back side of the integrated device die, the interconnect structure configured to deliver power between the power rail and the power delivery structure at the back side of the integrated device die.
Kim (Figs. 1, 3A, 4A, 4B and associated text) discloses one or more through mold vias (TMVs 305, 405) extending from a connector to an integrated voltage regulator die (item 105) and routing the power (paragraph 37), thus a power rail (TMVs 305, 405) extending through the insulating material …the power rail (TMVs 305, 405), and the back side of the integrated device die (item 103), the interconnect structure (item 173) configured to deliver power between the power rail (TMVs 305, 405) and the power delivery structure (items 171, 105) at the back side of the integrated device die (item 103).
Therefore it would have been obvious to one of ordinary skill in the art before the effective filing date to incorporate the teachings of Kim for the purpose of power distribution.
In regards to claim 25, Yang as modified by Kim does not specifically disclose wherein the insulating material comprises an inorganic dielectric.
In regards to claims 25, Yang (paragraph 83, Figs. 3G, 4 and associated text) discloses wherein the insulating material/encapsulant layer (items 384, 484) can be a molding compound, epoxy, or the like (paragraph 83). Examiner notes that is well known in the art that inorganic dielectrics can be used as encapsulants/insulating material/layers.
It would have been obvious to modify the invention to include an insulating material comprising inorganic dielectrics, since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use (In re Leshin, 125 USPQ 416).
In regards to claim 26, Yang (Figs. 3-5 and associated text and items) discloses further comprising a power delivery die (item 500a), wherein the power delivery die (item 500a) is hybrid bonded to the back surface interconnect structure (item 522).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Tong et al (US 2024/0128150 A1) discloses a backside power delivery network. Lu et al (US 2024/0063160 A1) and Patil et al. (US 2023/0035627 A1) both disclose a power delivery network/power rails, a reconstituted element and semiconductor die with circuitry. .
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TELLY D GREEN whose telephone number is (571)270-3204. The examiner can normally be reached M-F 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
TELLY D. GREEN
Examiner
Art Unit 2898
/TELLY D GREEN/Primary Examiner, Art Unit 2898 April 6, 2026
Prosecution Insights