Prosecution Insights
Last updated: October 02, 2026
Application No. 18/523,151

REFLOW PROTECTION FOR A MODULE SEMICONDUCTOR DEVICE

Final Rejection §102
Filed
Nov 29, 2023
Priority
Dec 29, 2022 — CN 202211710160.6
Examiner
NGUYEN, VAN THU T
Art Unit
2824
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Micron Technology Inc.
OA Round
4 (Final)
83%
Grant Probability
Favorable
5-6
OA Rounds
0m
Est. Remaining
89%
With Interview

Examiner Intelligence

Grants 83% — above average
83%
Career Allowance Rate
800 granted / 965 resolved
+14.9% vs TC avg
Moderate +6% lift
Without
With
+6.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
25 currently pending
Career history
998
Total Applications
across all art units

Statute-Specific Performance

§101
0.5%
-39.5% vs TC avg
§103
46.0%
+6.0% vs TC avg
§102
32.4%
-7.6% vs TC avg
§112
14.7%
-25.3% vs TC avg
Black line = Tech Center average estimate • Based on career data from 965 resolved cases

Office Action

§102
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This Office Action is in response to 08/10/2026 Amendment. Claims 1-19, and 21 are pending and examined. Claim 20 has been canceled. Claim 21 is newly added. Rejections of claims 13-14, 19 under 35 USC § 112 are withdrawn herein. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-19, 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 10,347,329 to Jean et al. (hereafter Jean). Regarding independent claim 1, Jean teaches a memory device (FIG. 6: memory device 600, which can be attached to a PCB using an infrared reflow (IR) operation, see 3:11-12), comprising: one or more components configured to: configure a reflow critical data region in a non-volatile memory that is associated with at least one reflow protection measure for data stored in the reflow critical data region (FIG. 6: configuring region SLC 602 for reflow protection mode, see 5:1-11), the non-volatile memory further associated with a non-reflow critical data region (FIG. 6: separate reflow critical data region SLC and non-reflow critical data region MLC portions in the memory device, see 3:22-29 and 5:41-48, 9:32-35); write a set of data to the reflow critical data region (i.e. storing data in region SLC 602), wherein the set of data is inherently associated with a module manufacture process, the non-volatile memory mounted to a module board during the module manufacture process (i.e. preloaded data, which includes firmware, a kernel, preloaded software, see 3:18-21 and 21:50-52. Preload data implies that data is loaded into the memory device before assembly of the memory device onto a PCB. The preload data is seen associated with manufacturing process of the memory device itself because the memory device has not been in use prior to assembly process on PCB); determine, at the memory device, that a reflow process associated with mounting the memory device to a carrier board has been completed (i.e. when the memory device receives indication from the host that a reflow soldering/heating/assembly is completed, see 5:1-11); and reconfigure the reflow critical data region to remove the at least one reflow protection measure based on determining that the reflow process associated with mounting the module board to the carrier board has been completed (memory cells used to store the data in the reflow-protection node can be reallocated from SLC to MLC after the assembly process on PCB, see 6:59-67). Regarding dependent claim 2, Jean teaches wherein the non-volatile memory is associated with multiple block groups, wherein a first block group, of the multiple block groups, is associated with the reflow critical data region before the reflow process has been completed, and wherein a second block group, of the multiple block groups, is associated with a non-reflow critical data region before the reflow process has been completed (FIG. 6: corresponding to SLC and TCL blocks). Regarding dependent claim 3, Jean teaches wherein the one or more components are further configured to write another set of data to the non-reflow critical data region (i.e. storing received data on remaining memory dies as MLC, see 6:49-58). Regarding dependent claim 4, Jean teaches wherein the at least one reflow protection measure includes storing the set of data using a single level cell mode prior to the reflow process associated with the memory device being completed (FIG. 6: configuring region SLC 602 for reflow protection mode prior to reflow, assembly, or manufacture, see 5:1-21). Regarding dependent claim 5, Jean teaches wherein removing the at least one reflow protection measure includes storing the set of data using a triple level cell mode (see 5:1-21). Regarding dependent claim 6, Jean teaches wherein the at least one reflow protection measure includes storing the set of data using altered threshold voltages prior to the reflow process associated with the memory device being completed (i.e. storing the set of data from SLC to MLC, see 5:1-21). Regarding dependent claim 7, Jean teaches wherein the one or more components are further configured to transmit, to the non-volatile memory, a clear reflow flag command, and wherein removing the at least one reflow protection measure is further based on the non-volatile memory receiving the clear reflow flag command (i.e. when the memory device can decide operation flow without receiving a separated indication of completed reflow or assembly from host, see 14:55-64 and claim 11. It is understood that the indication should be generated by the memory controller itself). Regarding dependent claim 8, Jean teaches wherein the one or more components are further configured to determine, at the memory device, that the reflow process associated with the memory device has been completed based on a clear reflow flag command included in a system boot image written to the non-volatile memory of the memory device after the reflow process has been completed (see 14:55-64 and claim 11). Regarding dependent claim 9, Jean teaches wherein the one or more components are further configured to write another system boot image to the non-volatile memory prior to the reflow process (such as firmware, see 3:7-21), and wherein the other system boot image implicitly does not include the clear reflow flag command (because the firmware is needed at booting prior to any running process). Regarding dependent claim 10, Jean implicitly teaches wherein the one or more components are further configured to determine, at the memory device, that the reflow process associated with the memory device has been completed based on a voltage level of a general purpose input/output of the memory device (see 14:55-64 and claim 11). Regarding independent claim 11, Jean teaches a module semiconductor device, comprising: a module board (see 4:20-39); a system on chip (SoC) component coupled to the module board (see 7:50-62); and one or more memory components coupled to the module board and communicatively connected to the SoC component, at least one of the SoC component or the one or more memory components (see FIG. 1) configured to: configure a reflow critical data region in a non-volatile memory that is associated with at least one reflow protection measure for data stored in the reflow critical data region (FIG. 6: configuring region SLC 602 for reflow protection mode, see 5:1-11), the non-volatile memory further associated with a non-reflow critical data region (FIG. 6: separate reflow critical data region SLC and non-reflow critical data region MLC portions in the memory device, see 3:22-29 and 5:41-48, 9:32-35); write a set of data to the reflow critical data region (i.e. storing data in region SLC 602), wherein the set of data is associated with a module manufacture process, the one or more memory components mounted to the module board during the module manufacture process (i.e. preloaded data, which includes firmware, a kernel, preloaded software, see 3:18-21 and 21:50-52. Preload data implies that data is loaded into the memory device before assembly of the memory device onto a PCB. The preload data is seen associated with manufacturing process of the memory device itself because the memory device has not been in use prior to assembly process on PCB); determine, at the at least one of the SoC component or the one or more memory components, that a reflow process associated with the memory device has been completed (i.e. when the memory device receives indication from the host that a reflow soldering/heating/assembly is completed, see 5:1-11); and reconfigure the reflow critical data region to remove the at least one reflow protection measure based on determining that the reflow process associated with mounting the module board to the carrier board has been completed (memory cells used to store the data in the reflow-protection node can be reallocated from SLC to MLC after the assembly process on PCB, see 6:59-67). Regarding dependent claim 12, Jean teaches wherein the at least one reflow protection measure includes at least one of: storing the set of data using a single level cell mode prior to the reflow process being completed (FIG. 6: configuring region SLC 602 for reflow protection mode prior to reflow, assembly, or manufacture, see 5:1-21), or storing the set of data using altered threshold voltages prior to the reflow process being completed (i.e. storing received data on remaining memory dies as MLC, see 6:49-58). Regarding dependent claim 13, Jean teaches wherein removing the at least one reflow protection measure is further based on the one or more memory components receiving a clear reflow flag command (i.e. when the host provides a flag to the memory device that a reflow soldering/heating/assembly is completed, the memory device switches from single-level or reflow protection mode to multi-level or normal operation mode, see 5:1-11). Regarding dependent claim 14, Jean implicitly teaches wherein the at least one of the SoC component or the one or more memory components are further configured to determine that the reflow process has been completed based on a signal received from a voltage source associated with the carrier board (when the host communicates with the memory device and send the flag via physical jack, see 17:5718). Regarding independent claim 15, Jean teaches a method, comprising: configuring, by one or more memory components of a module semiconductor device, a reflow critical data region in a non-volatile memory that is associated with at least one reflow protection measure for data stored in the reflow critical data region (FIG. 6: configuring region SLC 602 for reflow protection mode, see 5:1-11), the non-volatile memory further associated with a non-reflow critical data region (FIG. 6: separate reflow critical data region SLC and non-reflow critical data region MLC portions in the memory device, see 3:22-29 and 5:41-48, 9:32-35); writing, by the one or more memory components, a set of data to the reflow critical data region (i.e. storing data in region SLC 602), wherein the set of data is associated with a module manufacture process, the one or more memory components mounted to a module board during the module manufacture process (i.e. preloaded data, which includes firmware, a kernel, preloaded software, see 3:18-21 and 21:50-52. Preload data implies that data is loaded into the memory device before assembly of the memory device onto a PCB. The preload data is seen associated with manufacturing process of the memory device itself because the memory device has not been in use prior to assembly process on PCB); determining, by the one or more memory components of the module semiconductor device, that a reflow process associated with mounting the module semiconductor device to a carrier board has been completed (i.e. when the memory device receives indication from the host that a reflow soldering/heating/assembly is completed, see 5:1-11); and reconfiguring, by the one or more memory components, the reflow critical data region to remove the at least one reflow protection measure based on determining that the reflow process associated with mounting the module board to the carrier board has been completed (memory cells used to store the data in the reflow-protection node can be reallocated from SLC to MLC after the assembly process on PCB, see 6:59-67). Regarding dependent claim 16, Jean teaches writing, by the one or more memory components, another set of data to a non-reflow critical data region (i.e. storing received data on remaining memory dies as MLC, see 6:49-58). Regarding dependent claim 17, Jean teaches storing the set of data using a single level cell mode prior to the reflow process being completed (FIG. 6: configuring region SLC 602 for reflow protection mode prior to reflow, assembly, or manufacture, see 5:1-21); and storing the set of data using a triple level cell mode after the reflow process has been completed (i.e. storing the set of data from SLC to MLC, see 5:1-21). Regarding dependent claim 18, Jean teaches storing the set of data using altered threshold voltages prior to the reflow process being completed (i.e. storing received data on remaining memory dies as MLC, see 6:49-58). Regarding dependent claim 19, Jean teaches receiving, by the one or more memory components, a clear reflow flag command, wherein removing the at least one reflow protection measure is further based on the one or more memory components receiving the clear reflow flag command (i.e. when the host provides a flag to the memory device that a reflow soldering/heating/assembly is completed, the memory device switches from single level or reflow-protection mode to multi-level or normal operation mode, see 5:1-11). Regarding dependent claim 21, Jean implicitly teaches wherein configuring the reflow critical data region includes storing module-specific calibration data generated during a testing phase of the module manufacture process, wherein the module-specific calibration data is particular to a module semiconductor device comprising the non-volatile memory mounted to the module board (such as preloaded data of a kernel, wherein a kernel relates to memory management, device management which are inherently obtained when the memory device is tested during manufacturing process). Response to Arguments Applicant's arguments filed 08/10/2026 have been fully considered but they are not persuasive. Applicant argues: PNG media_image1.png 612 695 media_image1.png Greyscale Examiner respectfully disagrees. Jean implicitly suggests the amended limitations as Examiner explains in the body of rejections of claims 1, 11 and 15. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. September 18, 2026 /VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
Read full office action

Prosecution Timeline

Show 8 earlier events
Mar 23, 2026
Request for Continued Examination
Mar 26, 2026
Response after Non-Final Action
May 08, 2026
Non-Final Rejection mailed — §102
Jul 07, 2026
Interview Requested
Aug 04, 2026
Applicant Interview (Telephonic)
Aug 05, 2026
Examiner Interview Summary
Aug 10, 2026
Response Filed
Sep 22, 2026
Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

5-6
Expected OA Rounds
83%
Grant Probability
89%
With Interview (+6.4%)
2y 2m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 965 resolved cases by this examiner. Grant probability derived from career allowance rate.

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