Prosecution Insights
Last updated: August 30, 2026
Application No. 18/523,243

System and Method for Aligning Bonding Pads with Bonding Locations using Moiré Patterns

Non-Final OA §102
Filed
Nov 29, 2023
Examiner
ULLAH, ELIAS
Art Unit
2893
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Canon Inc.
OA Round
1 (Non-Final)
85%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
93%
With Interview

Examiner Intelligence

Grants 85% — above average
85%
Career Allowance Rate
724 granted / 853 resolved
+16.9% vs TC avg
Moderate +8% lift
Without
With
+7.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
25 currently pending
Career history
863
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
35.9%
-4.1% vs TC avg
§102
53.1%
+13.1% vs TC avg
§112
7.4%
-32.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 853 resolved cases

Office Action

§102
CTNF 18/523,243 CTNF 82021 08-08 AIA Restriction to one of the following inventions is required under 35 U.S.C. 121: I. Claim s 1-15 , drawn to a method of holding a chip on a chip chuck , classified in H10P72/0446 . II. Claim s 16-20 , drawn to a bonding system , classified in H10W80/163 . 08-21 Restriction for examination purposes as indicated is proper because all the inventions listed in this action are independent or distinct for the reasons given above and there would be a serious search and/or examination burden if restriction were not (a) the inventions have acquired a separate status in the art in view of their different classification; (b) the inventions have acquired a separate status in the art due to their recognized divergent subject matter; (c) the inventions require a different field of search (for example, searching different classes/subclasses or electronic resources, or employing different search queries); (d) the prior art applicable to one invention would not likely be applicable to another invention; (e) the inventions are likely to raise different non-prior art issues under 35 U.S.C. 101 and/or 35 U.S.C. 112, first paragraph. Applicant is advised that the reply to this requirement to be complete must include (i) an election of an invention to be examined even though the requirement may be traversed (37 CFR 1.143) and (ii) identification of the claims encompassing the elected invention . The election of an invention may be made with or without traverse. To reserve a right to petition, the election must be made with traverse. If the reply does not distinctly and specifically point out supposed errors in the restriction requirement, the election shall be treated as an election without traverse. Traversal must be presented at the time of election in order to be considered timely. Failure to timely traverse the requirement will result in the loss of right to petition under 37 CFR 1.144. If claims are added after the election, applicant must indicate which of these claims are readable upon the elected invention. Should applicant traverse on the ground that the inventions are not patentably distinct, applicant should submit evidence or identify such evidence now of record showing the inventions to be obvious variants or clearly admit on the record that this is the case. In either instance, if the examiner finds one of the inventions unpatentable over the prior art, the evidence or admission may be used in a rejection under 35 U.S.C. 103 or pre-AIA 35 U.S.C. 103(a) of the other invention. 08-23 AIA During a telephone conversation with Mr. Daniel Ratoff on May 20 th 2026 a provisional election was made with traverse to prosecute the invention of I , claim s 1-15 . Affirmation of this election must be made by applicant in replying to this Office action. Claim s 16-20 are withdrawn from further consideration by the examiner, 37 CFR 1.142(b), as being drawn to a non-elected invention. Claim Rejections - 35 USC § 102 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claims 1-3, 9 and 14-15 are r ejected under 35 U.S.C. 102(a )(1) as being a nticipated b y M inoda et al. (Minoda, US 2017/0329217). R egarding claim 1, Minoda sows a method comprising: holding a chip ( element 8 in FIG. 1) on a chip chuck ( element 5), wherein the chip (element 8) has a set of interconnect contacts (element 9/11); positioning a first grating (grating 31 as shown in FIG. 6A) relative to the set of interconnect contacts ( element 9/11); measuring a first moire pattern (see FIG. 1-3 and [0028]) of the first grating and the set of interconnect contacts; and adjusting position of the chip chuck relative to a substrate chuck based on the first moire pattern (see FIG. 1—3 and related text). Regarding claim 2, Minoda sows a method comprising, wherein the first grating has a grating pitch that is different from a contact pitch ([0064]) of the set of interconnect contacts (9/11). Regarding claim 3, Minoda sows a method, further comprising: receiving contact arrangement information about the set of interconnect contacts (element 9/11); and selecting the first grating from a group of gratings with different pitches based on the contact arrangement information (([0064]). Regarding claim 9, Minoda sows a method comprising, wherein adjusting the position of the chip chuck comprises: sending an instruction to a chip chuck stage to adjust the position of chip chuck relative to the substrate chuck (see FIG. 1-3). Regarding claim 14, Minoda sows a method, further comprising: bonding the chip to product substrate; and processing the substrate to manufacture a plurality of articles (see FIG. 1-3). Regarding claim 15, Minoda sows a method, further comprising, wherein the measuring and the adjusting are done repeatedly until the set of interconnect contacts are in a desired position based on the first moire pattern (see FIG. 1-3) . Allowable Subject Matter 12-151-08 AIA 07-43 12-51-08 Claim s 4-8 and 10-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ELIAS M ULLAH whose telephone number is (571)272-1415. The examiner can normally be reached M-F at 8AM-5PM EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Yara Green can be reached at 571-270-3035. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ELIAS ULLAH/Primary Examiner, Art Unit 2893 Application/Control Number: 18/523,243 Page 2 Art Unit: 2893 Application/Control Number: 18/523,243 Page 3 Art Unit: 2893 Application/Control Number: 18/523,243 Page 4 Art Unit: 2893 Application/Control Number: 18/523,243 Page 5 Art Unit: 2893 Application/Control Number: 18/523,243 Page 6 Art Unit: 2893
Read full office action

Prosecution Timeline

Nov 29, 2023
Application Filed
Jun 03, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12721016
DISPLAY PANEL, MANUFACTURING METHOD THEREOF AND DISPLAY APPARATUS
2y 6m to grant Granted Aug 25, 2026
Patent 12721123
INTEGRATION SOLUTION FOR NAND DEEP CONTACT GAP FILL
2y 7m to grant Granted Aug 25, 2026
Patent 12713939
PRE-MOLDED LEAD FRAMES FOR SEMICONDUCTOR PACKAGES
3y 2m to grant Granted Aug 18, 2026
Patent 12713984
SEMICONDUCTOR PACKAGE
3y 0m to grant Granted Aug 18, 2026
Patent 12708022
INTERCONNECT STRIPS
3y 10m to grant Granted Aug 11, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
85%
Grant Probability
93%
With Interview (+7.8%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 853 resolved cases by this examiner. Grant probability derived from career allowance rate.

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