DETAILED ACTION
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter. Claim 17 recites the details of lower trenches, including what they overlap and what they do not overlap. The combination of these limitations is not found in the prior art.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3-5, 7-11 & 19 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2015/0318261) by Chung et al (“Chung”) in view of (US-2017/0358558) by Lee et al (“Lee”).
Regarding claim 1, Chung discloses in FIG. 5 and related text, e.g., a semiconductor package (300) comprising:
a lower chip (340);
a chip stacked structure (various 309’s) arranged on the lower chip, the chip stacked structure comprising a plurality of upper chips (four 309’s are shown);
an underfill layer (317) disposed between the lower chip and the chip stacked structure and between the plurality of upper chips (see FIG. 5); and
a molding layer (319) surrounding the underfill layer and the chip stacked structure.
Chung does not disclose “wherein the lower chip has at least one lower trench positioned on an upper surface of the lower chip, and at least one of the plurality of upper chips has at least one upper trench positioned on an upper surface of the at least one of the plurality of upper chips”.
Lee discloses in FIG. 6 and related text, e.g., “wherein the lower chip (110; see par. 28) has at least one lower trench (150) positioned on an upper surface of the lower chip (see FIG. 6), and at least one of the plurality of upper chips (210/310/410) has at least one upper trench (250/350/450) positioned on an upper surface of the at least one of the plurality of upper chips”.
It would have been obvious to one of ordinary skill in the art at the time of the invention to modify the device of Chung with “wherein the lower chip has at least one lower trench positioned on an upper surface of the lower chip, and at least one of the plurality of upper chips has at least one upper trench positioned on an upper surface of the at least one of the plurality of upper chips” as taught by Lee, in order to allow for more area for underfill layer to occupy, thus resulting in a better control of underfill process, and in order to increase the surface area of chip, thus resulting in a better heat dissipation (due to heat dissipating from larger total area).
Regarding claim 3, the combined device of Chung and Lee disclose in cited figures and related text, e.g., wherein: the at least one upper trench overlaps the underfill layer in a vertical direction (see FIG. 6 of Lee; also compare to FIG. 5 of Chung; in both cases the limitations are met; hence, the limitations are met in combined device); and the at least one upper trench is filled with the underfill layer (see FIG. 6 of Lee).
Regarding claim 4, the combined device of Chung and Lee disclose in cited figures and related text, e.g., wherein each of the plurality of upper chips except for an uppermost chip of the plurality of upper chips includes the at least one upper trench (such an embodiment is disclosed in FIG. 1 of Lee, for example).
Regarding claim 5, the combined device of Chung and Lee disclose in cited figures and related text, e.g., wherein the at least one upper trenches of the plurality of upper chips overlap each other in a vertical direction (see FIG. 6 of Lee).
Regarding claim 7, the combined device of Chung and Lee disclose in cited figures and related text, e.g., wherein at least one of a cross section of the at least one lower trench and a cross section of the at least one upper trench has a shape selected from a quadrangular shape (see FIG. 6 of Lee), a triangular shape, and a U shape.
Regarding claim 8, the combined device of Chung and Lee disclose in cited figures and related text, e.g., wherein at least one of the at least one lower trench and the at least one upper trench comprises a plurality of trenches each having a circular shape in a plan view (see FIG. 5 of Lee and par. 51; it makes clear that even though squares are shown, the trenches may have “various shapes”; “circular shape” is one of the examples of basic shapes, and thus the “circular shape” is at the very least obvious in light of Lee’s explicit teachings), the plurality of trenches are arranged along an edge of the upper surface of the lower chip and an upper chip of the plurality of upper chips, respectively, to be spaced apart from each other (see FIGs. 5-6).
Regarding claim 9, the combined device of Chung and Lee disclose in cited figures and related text, e.g., wherein the at least one upper trench and the at least one lower trench have different shapes from each other in a plan view (see par. 51 of Lee; shapes not being the same shape is explicitly taught, without any limitations; thus, the above limitations are at the very least obvious in light of Lee’s explicit teachings).
Regarding claim 10, the combined device of Chung and Lee disclose in cited figures and related text, e.g., wherein: each of the lower chip and the chip stacked structure configures highband memory (HBM) (see pars. 23-24; such an arrangement is explicitly taught); and
each of the plurality of upper chips of the chip stacked structure comprises dynamic random access memory (DRAM) (see pars. 23-24; such an arrangement is explicitly taught).
Regarding claim 11, the combined device of Chung and Lee disclose in cited figures and related text, e.g., wherein the lower chip and at least some of the plurality of upper chips comprise through electrodes (FIG. 5 of Chung, 315 and FIG. 6 of Lee, 130) penetrating the lower chip and the at least some of the plurality of upper chips (see the cited figures), respectively, in a vertical direction.
Regarding claim 19, the combined device of Chung and Lee disclose in cited figures and related text, e.g., a semiconductor package comprising:
a package substrate (FIG. 5 of Chung, 100);
a redistribution structure (inside 200) arranged on the package substrate;
a sub-semiconductor package (300) arranged on the redistribution structure; and
a semiconductor chip (400) arranged on the redistribution structure and spaced apart from the sub-semiconductor package in a horizontal direction, wherein the sub-semiconductor package comprises a lower chip (see claim 1), a chip stacked structure arranged on the lower chip (see claim 1), the chip stacked structure comprising a plurality of upper chips (see claim 1), an underfill layer disposed between the lower chip and the chip stacked structure and between the plurality of upper chips (see claim 1), and a molding layer surrounding the underfill layer and the chip stacked structure (see claim 1), wherein the lower chip has at least one lower trench positioned on an upper surface of the lower chip (see claim 1), and at least one of the plurality of upper chips has at least one upper trench positioned on an upper surface of the at least one of the plurality of upper chips (see claim 1).
Claims 2, 12, 14-16, 18 & 20 are rejected under 35 U.S.C. 103 as being unpatentable over (US-2015/0318261) by Chung et al (“Chung”) in view of (US-2017/0358558) by Lee et al (“Lee”) as applied to claim(s) above, and further in view of (US-2020/0343198) by Tsai et al (“Tsai”).
Regarding claim 2, Chung and Lee disclose substantially the entire claimed structure as recited in above claims, except “a portion of the at least one lower trench overlaps the molding layer in a vertical direction, and a remaining portion of the at least one lower trench overlaps the underfill layer in the vertical direction, the portion of the at least one lower trench overlapping the molding layer in the vertical direction is filled with the molding layer; and the remaining portion of the at least one lower trench overlapping the underfill layer in the vertical direction is filled with the underfill layer”.
Tsai discloses in FIG. 1M and related text, e.g., “a portion of the at least one lower trench (123) overlaps the molding layer (170, see par. 60) in a vertical direction (see FIG. 1M), and a remaining portion of the at least one lower trench overlaps the underfill layer (160) in the vertical direction (see FIG. 1M), the portion of the at least one lower trench overlapping the molding layer in the vertical direction is filled with the molding layer (see FIG. 1M); and
the remaining portion of the at least one lower trench overlapping the underfill layer in the vertical direction is filled with the underfill layer (see FIG. 1M).”
It would have been obvious to one of ordinary skill in the art at the time of the invention to further modify the device of Chung and Lee with “a portion of the at least one lower trench overlaps the molding layer in a vertical direction, and a remaining portion of the at least one lower trench overlaps the underfill layer in the vertical direction, the portion of the at least one lower trench overlapping the molding layer in the vertical direction is filled with the molding layer; and the remaining portion of the at least one lower trench overlapping the underfill layer in the vertical direction is filled with the underfill layer” as taught by Tsai, in order to simplify the processing steps of making the packaged device, by preventing the underfill layer from reaching the scribe line, thus shrinkage volume of the underfill layer is reduced and warpage of package due to thermal expansion mismatch is also reduced (see par. 65).
Regarding claim 12, the combined device of Chung, Lee and Tsai disclose in cited figures and related text, e.g., a semiconductor package comprising:
a lower chip (see claim 1);
a chip stacked structure arranged on the lower chip, the chip stacked structure comprising a plurality of upper chips (see claim 1);
an underfill layer disposed between the lower chip and the chip stacked structure and between the plurality of upper chips (see claim 1); and
a molding layer surrounding the underfill layer and the chip stacked structure (see claim 1), wherein the lower chip has at least one lower trench positioned on an upper surface of the lower chip (see claim 1), a portion of the at least one lower trench overlaps the molding layer in a vertical direction (see claim 2), and a remaining portion of the at least one lower trench overlaps the underfill layer in the vertical direction (see claim 2), and the portion of the at least one lower trench overlapping the molding layer in the vertical direction is filled with the molding layer (see claim 2), and the remaining portion of the at least one lower trench overlapping the underfill layer in the vertical direction is filled with the underfill layer (see claim 2).
Regarding claim 14, the combined device of Chung, Lee and Tsai disclose in cited figures and related text, e.g., wherein a cross section of the at least one lower trench has a shape selected from a quadrangular shape, a triangular shape, and a U shape (see claim 7).
Regarding claim 15, the combined device of Chung, Lee and Tsai disclose in cited figures and related text, e.g., wherein: the at least one lower trench comprises a plurality of trenches arranged along an edge of the upper surface of the lower chip to be spaced apart from each other (see FIG. 5 of Lee; it shows a two trench variant); and
each of the plurality of trenches has a circular shape in a plan view (see claim 8; such an arrangement is at the very least obvious in light of Lee’s explicit teachings).
Regarding claim 16, the combined device of Chung, Lee and Tsai disclose in cited figures and related text, e.g., wherein a plurality of lower trenches are arranged in two rows along the edge of the upper surface of the lower chip in a plan view (see FIG. 5 of Lee).
Regarding claim 18, the combined device of Chung, Lee and Tsai disclose in cited figures and related text, e.g., wherein a vertical length of the at least one lower trench is in a range of about 1 um to about 500 um (see par. 33 of Tsai).
Regarding claim 20, the combined device of Chung, Lee and Tsai disclose in cited figures and related text, e.g., wherein: a portion of the at least one lower trench overlaps the molding layer in a vertical direction (see claim 2), and a remaining portion of the at least one lower trench overlaps the underfill layer in the vertical direction (see claim 2);
the portion of the at least one lower trench overlapping the molding layer in the vertical direction is filled with the molding layer (see claim 2), and the remaining portion of the at least one lower trench overlapping the underfill layer in the vertical direction is filled with the underfill layer (see claim 2); and
each of the lower chip and the chip stacked structure configures highband memory (HBM), and each of the plurality of upper chips of the chip stacked structure comprises dynamic random access memory (DRAM) (see claim 10).
Conclusion
Additional references (if any) are cited on the PTO-892 as disclosing similar features to those of the instant invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alexander Belousov whose telephone number is (571)-272-3167. The examiner can normally be reached on 10 am-4 pm. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Alexander Belousov/Patent Examiner, Art Unit 2894
09/27/26
/JEFF W NATALINI/Supervisory Patent Examiner, Art Unit 2818
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