DETAILED ACTION
This office action is in response to amendment filed 9/2/2026.
Claims 1-4, 8-9, 12-13, and 17-20 are pending. Claims 5-7, 10-11, and 14-16 have been canceled. Claim 20 is new. Claim 1 has been amended.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-4, 8-9, 12-13, and 17-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 reciting “a first transfer transistor … that is configured to transfer signal charged generated in the first photoelectric conversion circuit to the floating diffusion, and a second transfer transistor … that configured to transfer signal charge generated in the second photoelectric conversion circuit to the floating diffusion; … a single polysilicon member is shared by a gate of the first transfer transistor and a gate of the second transfer transistor, … and wherein the floating diffusion is arranged in a region surrounded by the single polysilicon member” lacks adequate written description and recites new matter.
More specifically, Applicant discloses in some embodiment, e.g. FIGs. 7-10 of non-elected Species II, two transfer transistors TX transferring signal charge to one common floating diffusion FD. However, in such embodiment, the gates of the transfer transistors TX are formed by two separate polysilicon members.
Applicant also discloses in some embodiment, e.g. FIGs. 23-25 of elected Species IX, where the gates of the transfer transistors are formed by a single polysilicon member, and wherein the single polysilicon member surrounds the plurality of floating diffusions. However, in such embodiment, the transfer transistors transfer signal charge to different floating diffusions.
However, the newly claimed combination reciting a floating diffusion being surrounded by the single polysilicon member, and the first and second transfer transistors transferring signal charges to the same floating diffusion surrounded by the single polysilicon member is not described by Applicant’s original disclosure. There is no clear and unequivocal support for the amended claim.
Other claims are rejected for depending on a rejected claim.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 13, and 17-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Machida WO 2022/102471 A1 (related publication US 2024/0006431 A1 is referenced below for translation purposes) in view of Jin US 2023/0071106 A1.
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In re claim 1, Machida discloses (e.g. FIGs. 1-9) a photoelectric conversion apparatus comprising:
a first component 10 comprising:
a first semiconductor substrate 11 having a first plane (top) and a second plane (bottom) facing the first plane,
a first photoelectric conversion circuit PD1 configured to receive light from the second plane (bottom),
a second photoelectric conversion circuit PD2 configured to receive light from the second plane (bottom),
a floating diffusion FD,
a first transfer transistor TR (corresponding to sensor pixel with PD1) that is provided on a side where the first (top) plane is provided and that is configured to transfer signal charge generated in the first photoelectric conversion circuit PD1 to the floating diffusion FD (¶ 77), and
a second transfer transistor TR (corresponding to sensor pixel with PD2) that is provided on the side where the first (top) plane is provided and that is configured to transfer signal charge generated in the second photoelectric conversion circuit PD2 to the floating diffusion FD (¶ 77); and
a second component 20 comprising:
a second semiconductor substrate 21 having a third plane and a fourth plane facing the third plane,
an insulator 51 (including 53) configured to penetrate through the second semiconductor substrate 20 from the third plane to the fourth plane or from the fourth plane to the third plane (¶ 105),
a first amplification transistor AMP (e.g. of one readout circuit 22, see FIGs. 2-3, ¶ 79) configured to receive a signal via the first transfer transistor TR, and a second amplification transistor AMP (of another readout circuit 22, see FIGs. 2-3, ¶ 79) configured to receive a signal via the second transfer transistor TR, the second component 20 being stacked on the first component 10,
wherein a single polysilicon member (¶ 92) is shared by a gate TG of the first transfer transistor TR and a gate TG of the second transfer transistor TR (see FIG. 3 showing a common gate, e.g. TG1, shared by four sensor pixels),
wherein a through-electrode (another through-substrate similar to 54 connected to TG, see FIG. 9, ¶ 107) penetrates through the insulator 51,53 and is electrically connected to the single polysilicon member TG, and
wherein the floating diffusion FD is arranged in a region surrounded (e.g. partially surrounded) by the single polysilicon member TG.
Machida discloses a common floating diffusion being partially surrounded by a polysilicon gate member that is shared by plural transfer transistors. E.g. FIGs. 4, 11 and 12 shows FD1 is partially surrounded by TG1, TG2, TG3, TG4. Claim does not require a common floating diffusion to be “completely surrounded” by the same single polysilicon member in plan view.
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Furthermore, Jin teaches (e.g. FIGs. 1-4) an image sensor, wherein four sensing pixels 40 sharing a common floating diffusion FD 80, and a common ring shaped transfer gate TG 50 is formed to completely surround the floating diffusion FD 80 in plan view, and the ring shaped transfer gate is shared by the four transfer transistors (see FIG. 4, ¶ 67). Jin teaches ring shaped transfer gate TG 50 more effectively generate an electric field for transferring charged from the sensing element 40 to the floating diffusion FD 80 (¶ 69).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to Machida’s transfer gates as a ring shaped transfer gate to completely surround a floating diffusion as taught by Jin to more effectively generate an electric field for transferring charged from the sensing element.
In re claim 2, Machida discloses (e.g. FIGs. 3 & 4) wherein the first transfer transistor TR (associated with PD1 and TG1) and the second transfer transistor TR (associated with PD2 and TG1) are controlled by a common control signal (e.g. common TG1).
Jin discloses (e.g. FIG. 4) wherein the first transfer transistor and the second transfer transistor are controlled by a common control signal (e.g. common transfer gate TG 50).
In re claim 3, Machida discloses (e.g. FIGs. 3 & 4) wherein the floating diffusion includes a first floating diffusion FD1 and a second floating diffusion FD2,
wherein signal charge generated in the first photoelectric conversion circuit PD1 (coupled to TG1) is transferred to the first floating diffusion FD1, and
wherein signal charge generated in the second photoelectric conversion circuit PD2 (coupled to same TG1) is transferred to the second floating diffusion FD2.
Furthermore, first floating diffusion and second floating diffusion may be different portions of the common floating diffusion FD taught by Machida and Jin.
In re claim 13, Machida discloses (e.g. FIG. 3) wherein a first group of transfer transistors (e.g. TR for PD1 and PD3 associated with TG1) composed of a plurality of transfer transistors including the first transfer transistor is controlled by a first control signal TG1, and
wherein a second group of transfer transistors (e.g. TR for PD2 and PD4 associated with TG1) composed of a plurality of transfer transistors including the second transfer transistor is controlled by the first control signal TG1.
Jin discloses (e.g. FIG. 4) wherein a first group of transfer transistors (transfer transistors for top two sensing elements 40) composed of a plurality of transfer transistors including the first transfer transistor is controlled by a first control signal (applied to TG 50), and
wherein a second group of transfer transistors (transfer transistors for bottom two sensing elements 40) composed of a plurality of transfer transistors including the second transfer transistor is controlled by the first control signal (applied to common TG 50).
In re claim 17, Machida discloses (e.g. FIG. 9) wherein the first component 10 has a first wiring layer (including wirings in insulating 46) at the first (top) plane.
In re claim 18, Machida discloses (e.g. FIG. 22) a photoelectric conversion system comprising:
the photoelectric conversion apparatus 303 according to claim 1 (¶ 154); and
a signal processing circuit 305 configured to generate an image using a signal output by the photoelectric conversion apparatus (¶ 159).
In re claim 19, Machida discloses (e.g. FIGs. 23-24) a moving object (e.g. automobiles, ¶ 163) including the photoelectric conversion apparatus according to claim 1 (applied in imaging section 7410, ¶ 191), the moving object comprising:
a controller 7600 configured to control movement of the moving object using a signal output by the photoelectric conversion apparatus (¶ 191-192).
In re claim 20, Machida discloses (e.g. FIG. 4) wherein the single polysilicon member (e.g. TG1, ¶ 92) functions as the gate of the first transfer transistor and the gate of the second transfer transistor.
Jin discloses (e.g. FIG. 4) wherein the single gate member 50 functions as the gate of the first transfer transistor and the gate of the second transfer transistor (¶ 67-69).
Claims 4, 8, 9, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Machida and Jin as applied to claim 1-3 above, and further in view of Hynecek et al. US 9,888,197 B1 (Hynecek).
In re claim 4, Machida discloses (e.g. FIGs. 1-3) the claimed invention including amplification transistor AMP in each readout pixel 22 that receives signal via the respective transfer transistor TR coupled to the photoelectric conversion unit PD, wherein the amplification transistors are provided in the second component 20.
Machida does not explicitly disclose wherein a source or drain of the first amplification transistor is connected to a first signal holding circuit and a third amplification transistor, and wherein a source or drain of the second amplification transistor is connected to a second signal holding circuit and a fourth amplification transistor.
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Hynecek discloses (e.g. FIGs. 1-3) a photoelectric conversion apparatus comprising a first component 200 including photoelectric conversion circuits 305 and transfer transistors 310, a second component 205 including first/second amplification transistors 315 amplifying signal for respective pixels. Hynecek further discloses a third component 210 further comprising a feedback network 330 including third/fourth amplification transistors 355 and signal holding circuits 350, wherein a source or drain of the first/second amplification transistor 315 is connected (through interconnects 245) to a first/second signal holding circuit 350 and a third/fourth amplification transistor 355. Hynecek teaches the feedback network 330 stabilizes the common-mode voltage of the first/second amplifying device 315 (Column 6, lines 27-39).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further provide a feedback network having further amplification transistors and signal holding circuits as taught by Hynecek that couples to each of Machida’s readout circuits 22 so as to stabilize the common-mode voltage of the first/second amplifying transistors AMP.
In re claim 8, Hynecek discloses (FIG. 3) wherein a control signal controlling the third amplification transistor 355 (associated with one pixel unit 305) is different from a control signal controlling the fourth amplification transistor 355 (associated with a different pixel unit 305).
In re claim 9, Hynecek discloses (e.g. FIGs. 2-3) further comprising:
a third component 210 comprising:
a third semiconductor substrate having a fifth plane and a sixth plane facing the fifth plane, and include the first signal holding circuit 350 (associated with one pixel unit 305), the second signal holding circuit 350 (associated with a different pixel unit 305), the third amplification transistor 355 (associated with the one pixel unit 305), and the fourth amplification transistor 355 (associated with the different pixel unit 305).
In re claim 12, Machida discloses (e.g. FIG. 9) wherein the first component 10 has a first wiring layer (including wirings in insulating 46) at the first (top) plane.
Response to Arguments
Applicant's arguments filed 9/2/2026 have been fully considered but they are not persuasive.
Regarding Machida, Applicant argues the floating diffusion is arranged outside a region surrounded by the single polysilicon member (Remark, page 9).
This is not persuasive. Claim does not require the floating diffusion to be “completely surrounded” by the single polysilicon member in plan view. Machida discloses a common floating diffusion that is partially surrounded by a polysilicon gate member that is shared by plural transfer transistors. Machida’s FIGs. 4, 11 and 12 shows FD1 is partially surrounded by TG1, TG2, TG3, TG4.
Furthermore, Jin teaches (e.g. FIGs. 1-4) an image sensor, wherein four sensing pixels 40 sharing a common floating diffusion FD 80, and a common ring shaped transfer gate TG 50 is formed to completely surround the floating diffusion FD 80 in plan view, and the ring shaped transfer gate is shared by the four transfer transistors (see FIG. 4, ¶ 67). Jin teaches ring shaped transfer gate TG 50 more effectively generate an electric field for transferring charged from the sensing element 40 to the floating diffusion FD 80 (¶ 69).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to Machida’s transfer gates as a ring shaped transfer gate to completely surround a floating diffusion as taught by Jin to more effectively generate an electric field for transferring charged from the sensing element.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET.
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/YU CHEN/Primary Examiner, Art Unit 2896
YU CHEN
Examiner
Art Unit 2896
Prosecution Insights