Prosecution Insights
Last updated: July 17, 2026
Application No. 18/523,353

PHOTOELECTRIC CONVERSION APPARATUS AND DEVICE HAVING STACKED COMPONENTS

Non-Final OA §102§103§112
Filed
Nov 29, 2023
Priority
Nov 30, 2022 — JP 2022-190917
Examiner
CHEN, YU
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Canon Inc.
OA Round
1 (Non-Final)
68%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 68% — above average
68%
Career Allowance Rate
727 granted / 1071 resolved
At TC average
Strong +30% interview lift
Without
With
+29.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 10m
Avg Prosecution
80 currently pending
Career history
1176
Total Applications
across all art units

Statute-Specific Performance

§101
0.8%
-39.2% vs TC avg
§103
76.9%
+36.9% vs TC avg
§102
12.4%
-27.6% vs TC avg
§112
5.4%
-34.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1071 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Election/Restrictions Applicant’s election without traverse of Species IX (FIGs. 23-25) in the reply filed on 2/27/2026 is acknowledged. Applicant indicates claims 1-4, 8-11, 13-14, 16 and 18-19 as encompassing the elected species. However, upon further examination, claims 10 and 14 recites features of non-elected species. More specifically, claim 10 recites “wherein bonding portions that are configured to electrically connect the first component and the second component to each other are smaller in number than bonding portions that are configured to electrically connect the second component and the third component to each other”. As shown in FIGs. 23-25 of the elected species, the bonding portions between appear to be same. The number of metal bondings is disclosed to be reduced for embodiment shown in FIGs. 27-29 (see ¶ [0125] & [0127]) directed to non-elected Species XI. Claim 14 reciting “wherein a direction in which the plurality of transfer transistors included in the first group of transfer transistors are arranged intersects with a direction in which a plurality of the floating diffusions to which the plurality of transfer transistors included in the first group of transfer transistors is connected in a respective manner, and wherein the plurality of floating diffusions is smaller in number than the plurality of transfer transistors”. However, as shown in FIGs. 23-25 of the elected species, the number of floating diffusions and transfer transistors is the same, i.e. one floating diffusion FD associated with each transfer transistor TX. Shared floating diffusion FD is disclosed in FIG. 7-10 directed to non-elected Species II and III. Claims 12 and 17, on the other hand, generically reciting a first wiring layer in the first component do read on the elected species. Therefore, claims 12 and 17 are rejoined for examination, while claims 10 and 14 are withdrawn from consideration in addition to claims 5-7 and 15. Claims 5-7, 10, and 14-15 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 2/27/2026. Drawings The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “201” (¶ [0075]). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: “422” (FIGs. 5B, 12B, 24B, 29B). Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claims 1-3, 11-13, and 16-19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention. Claim 1 reciting “a polysilicon member that is a gate of the first transfer transistor is a gate of the second transfer transistor, and a through-electrode configured to penetrate through the insulator and the polysilicon member are electrically connected to each other” renders the claim indefinite. Firstly, it is unclear how is the gate first transfer transistor also a gate of the second transfer transistor. If the polysilicon member is defined as the gate of the first transfer transistor, it is unclear how can it be simultaneously a gate of the second transistor. Furthermore, it is unclear what “are electrically connected to each other”. Only one through-electrode is claimed. The one through-electrode is “electrically connected” to what? Claims 11 and 16 reciting “wherein a voltage is supplied to the first transfer transistor via the second semiconductor substrate” renders the claims indefinite. It is unclear how is a voltage supplied to the first transfer transistor “via the second semiconductor substrate”. The second semiconductor substrate is not described as conductive and transmit voltage signal. Other claims are rejected for depending on a rejected claim. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 11-13, and 16-19 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Machida WO 2022/102471 A1 (related publication US 2024/0006431 A1 is referenced below for translation purposes). PNG media_image1.png 742 596 media_image1.png Greyscale In re claim 1, as best understood, Machida discloses (e.g. FIGs. 1-9) a photoelectric conversion apparatus comprising: a first component 10 comprising: a first semiconductor substrate 11 having a first plane (top) and a second plane (bottom) facing the first plane, a first photoelectric conversion circuit PD1 configured to receive light from the second plane (bottom), a second photoelectric conversion circuit PD2 configured to receive light from the second plane (bottom), a floating diffusion FD, a first transfer transistor TR (corresponding to sensor pixel with PD1) that is provided on a side where the first (top) plane is provided and that is configured to transfer signal charge generated in the first photoelectric conversion circuit PD1 to the floating diffusion FD (¶ 77), and a second transfer transistor TR (corresponding to sensor pixel with PD2) that is provided on the side where the first (top) plane is provided and that is configured to transfer signal charge generated in the second photoelectric conversion circuit PD2 to the floating diffusion FD (¶ 77); and a second component 20 comprising: a second semiconductor substrate 21 having a third plane and a fourth plane facing the third plane, an insulator 53 configured to penetrate through the second semiconductor substrate 20 from the third plane to the fourth plane or from the fourth plane to the third plane (¶ 105), a first amplification transistor AMP (e.g. of one readout circuit 22, see FIGs. 2-3, ¶ 79) configured to receive a signal via the first transfer transistor TR, and a second amplification transistor AMP (of another readout circuit 22, see FIGs. 2-3, ¶ 79) configured to receive a signal via the second transfer transistor TR, the second component 20 being stacked on the first component 10, “wherein a polysilicon member (¶ 91) that is a gate TG of the first transfer transistor TR is a gate TG of the second transfer transistor TR (as best understood, the gates TG of the transfer transistors are formed from the same polysilicon member; furthermore, see FIG. 3 showing a common gate, e.g. TG1, for four sensor pixels), and a through-electrode 54 (see FIG. 9) configured to penetrate through the insulator 53 and the polysilicon member TG (54 extends through at least the planar portion of polysilicon gates TG, see FIG. 9) are electrically connected to each other” (as best understood, the through-electrode 54 is electrically connected to the floating diffusion FD of the transfer transistors TX). In re claim 2, Machida discloses (e.g. FIGs. 3 & 4) wherein the first transfer transistor TR (associated with PD1 and TG1) and the second transfer transistor TR (associated with PD2 and TG1) are controlled by a common control signal (e.g. common TG1). In re claim 3, Machida discloses (e.g. FIGs. 3 & 4) wherein the floating diffusion includes a first floating diffusion FD1 and a second floating diffusion FD2, wherein signal charge generated in the first photoelectric conversion circuit PD1 (coupled to TG1) is transferred to the first floating diffusion FD1, and wherein signal charge generated in the second photoelectric conversion circuit PD2 (coupled to same TG1) is transferred to the second floating diffusion FD2. In re claim 11, as best understood, Machida discloses (e.g. FIG. 9) wherein a voltage is supplied to the first transfer transistor TR “via the second semiconductor substrate 21” (as best understood, voltage is supplied via wiring 54 which extends through second semiconductor substrate 21). In re claim 12, Machida discloses (e.g. FIG. 9) wherein the first component 10 has a first wiring layer (including wirings in insulating 46) at the first (top) plane. In re claim 13, Machida discloses (e.g. FIG. 3) wherein a first group of transfer transistors (e.g. TR for PD1 and PD3 associated with TG1) composed of a plurality of transfer transistors including the first transfer transistor is controlled by a first control signal TG1, and wherein a second group of transfer transistors (e.g. TR for PD2 and PD4 associated with TG1) composed of a plurality of transfer transistors including the second transfer transistor is controlled by the first control signal TG1. In re claim 16, as best understood, Machida discloses (e.g. FIG. 9) wherein a voltage is supplied to the first transfer transistor TR “via the second semiconductor substrate 21” (as best understood, voltage is supplied via wiring 54 which extends through second semiconductor substrate 21). In re claim 17, Machida discloses (e.g. FIG. 9) wherein the first component 10 has a first wiring layer (including wirings in insulating 46) at the first (top) plane. In re claim 18, Machida discloses (e.g. FIG. 22) a photoelectric conversion system comprising: the photoelectric conversion apparatus 303 according to claim 1 (¶ 154); and a signal processing circuit 305 configured to generate an image using a signal output by the photoelectric conversion apparatus (¶ 159). In re claim 19, Machida discloses (e.g. FIGs. 23-24) a moving object (e.g. automobiles, ¶ 163) including the photoelectric conversion apparatus according to claim 1 (applied in imaging section 7410, ¶ 191), the moving object comprising: a controller 7600 configured to control movement of the moving object using a signal output by the photoelectric conversion apparatus (¶ 191-192). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 4, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Machida as applied to claim 1-3 above, and further in view of Hynecek et al. US 9,888,197 B1 (Hynecek). In re claim 4, Machida discloses (e.g. FIGs. 1-3) the claimed invention including amplification transistor AMP in each readout pixel 22 that receives signal via the respective transfer transistor TR coupled to the photoelectric conversion unit PD, wherein the amplification transistors are provided in the second component 20. Machida does not explicitly disclose wherein a source or drain of the first amplification transistor is connected to a first signal holding circuit and a third amplification transistor, and wherein a source or drain of the second amplification transistor is connected to a second signal holding circuit and a fourth amplification transistor. PNG media_image2.png 632 954 media_image2.png Greyscale Hynecek discloses (e.g. FIGs. 1-3) a photoelectric conversion apparatus comprising a first component 200 including photoelectric conversion circuits 305 and transfer transistors 310, a second component 205 including first/second amplification transistors 315 amplifying signal for respective pixels. Hynecek further discloses a third component 210 further comprising a feedback network 330 including third/fourth amplification transistors 355 and signal holding circuits 350, wherein a source or drain of the first/second amplification transistor 315 is connected (through interconnects 245) to a first/second signal holding circuit 350 and a third/fourth amplification transistor 355. Hynecek teaches the feedback network 330 stabilizes the common-mode voltage of the first/second amplifying device 315 (Column 6, lines 27-39). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to further provide a feedback network having further amplification transistors and signal holding circuits as taught by Hynecek that couples to each of Machida’s readout circuits 22 so as to stabilize the common-mode voltage of the first/second amplifying transistors AMP. In re claim 8, Hycenek discloses (FIG. 3) wherein a control signal controlling the third amplification transistor 355 (associated with one pixel unit 305) is different from a control signal controlling the fourth amplification transistor 355 (associated with a different pixel unit 305). In re claim 9, Hycenek discloses (e.g. FIGs. 2-3) further comprising: a third component 210 comprising: a third semiconductor substrate having a fifth plane and a sixth plane facing the fifth plane, and include the first signal holding circuit 350 (associated with one pixel unit 305), the second signal holding circuit 350 (associated with a different pixel unit 305), the third amplification transistor 355 (associated with the one pixel unit 305), and the fourth amplification transistor 355 (associated with the different pixel unit 305). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to YU CHEN whose telephone number is (571)270-7881. The examiner can normally be reached Monday-Friday: 9AM-5PM ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, WILLIAM KRAIG can be reached on 5712728660. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /YU CHEN/Primary Examiner, Art Unit 2896 YU CHEN Examiner Art Unit 2896
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Prosecution Timeline

Nov 29, 2023
Application Filed
Apr 13, 2026
Examiner Interview (Telephonic)
Apr 23, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
68%
Grant Probability
98%
With Interview (+29.6%)
2y 10m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1071 resolved cases by this examiner. Grant probability derived from career allowance rate.

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