DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Shimada 20240313022 in view of Miyajima et al. 20100282948 further in view of Kasukawa (202500721400)
Regarding Claim 1, in Fig 7 paragraph 0132 and Fig. 11 paragraph 0146, along with paragraph 0170-183 (SPAD) Shimada et al. discloses photoelectric conversion apparatus including an avalanche photodiode, the apparatus comprising: a semiconductor layer having a first surface and a second surface; a first semiconductor region of a first conductivity type disposed at a first depth; a second semiconductor region of a second conductivity type disposed at a second depth that is greater than the first depth from the first surface, wherein the second semiconductor region forms the avalanche photodiode together with the first semiconductor region; a third semiconductor region of the first conductivity type provided in contact with an end portion of the first semiconductor region; an oxide film disposed on the first surface of the semiconductor layer. (Please note that element 371 is a polysilicon TFT in Shiamada); Shimada fails to disclose the limitation where a member provided on an opposite side of the oxide film from the semiconductor layer in cross-sectional view; wiring; and a contact plug configured to connect the wiring to the first surface of the semiconductor layer, wherein the member is disposed to overlap at least a boundary between the first semiconductor region and the third semiconductor region in plan view, wherein the member is disposed between the wiring and the semiconductor layer, and wherein a work function of the member differs from a work function of each of the first semiconductor region and the third semiconductor region so that a potential gradient for signal charge is generated in a depth direction of the semiconductor layer at at least the boundary. However, Miyajima eta l. discloses an avalanche photodiode where in paragraphs 0073, 0074, 0076, the required member (n/p doped polysilicon) is disclosed. Furthermore, Kasukawa discloses an avalanche photodiode where in paragraph 0172 along with paragraphs 0125, 0126, 0127, 0153, 0154 and 0255, the required workfunction/potential gradient is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required member and potential gradient in Shimada as taught by Miyajima and Kasukawa, respectively, in order to increase the performance of the avalanche photodiode.
Regarding Claim 2, in Shimada, Miyajima et al. and Kasukawa combination, wherein the member is made of polysilicon of the second conductivity type.
Regarding Claim 3, in Shimada, Miyajima et al. and Kasukawa combination, wherein the first conductivity type is an N type, and wherein the work function of the member is greater than the work function of each of the first semiconductor region and the third semiconductor region.
Regarding Claim 4, in Shimada, Miyajima et al. and Kasukawa combination, wherein the member is made of P-type polysilicon.
Regarding Claim 5, in Shimada, Miyajima et al. and Kasukawa combination, wherein the first conductivity type is a P type, and wherein the work function of the member is less than the work function of each of the first semiconductor region and the third semiconductor region.
Regarding Claim 6, in Shimada, Miyajima et al. and Kasukawa combination, wherein the member is made of N-type polysilicon.
Regarding Claim 7, in Shimada, Miyajima et al. and Kasukawa combination, a first wiring portion electrically connected to the first semiconductor region; and a second wiring portion electrically connected to the second semiconductor region, wherein the first wiring portion is electrically connected to the member.
Regarding Claim 8, in Shimada, Miyajima et al. and Kasukawa combination, wherein the member overlaps the entire first semiconductor region in plan view.
Regarding Claim 9, in Shimada, Miyajima et al. and Kasukawa combination, wherein the member overlaps the entire third semiconductor region in plan view.
Regarding Claim 10, in Shimada, Miyajima et al. and Kasukawa combination, further comprising: a protective film provided on the oxide film; and an interlayer film provided on the protective film, wherein the member is disposed between the protective film and the interlayer film.
Regarding Claim 11, in Fig 7 paragraph 0132 and Fig. 11 paragraph 0146, along with paragraph 0170-183 (SPAD), Shimada et al. discloses a photoelectric conversion apparatus having an avalanche photodiode, the apparatus comprising: a semiconductor layer having a first surface and a second surface; a first semiconductor region of a first conductivity type disposed at a first depth; a second semiconductor region of a second conductivity type disposed at a second depth that is greater than the first depth from the first surface, wherein the second semiconductor region forms the avalanche photodiode together with the first semiconductor region; a third semiconductor region of the first conductivity type provided in contact with an end portion of the first semiconductor region; an oxide film disposed on the first surface of the semiconductor layer; a protective film disposed on an opposite side of the oxide film from the semiconductor layer, wherein the protective film is made of a material that differs from a material used for the oxide film; an interlayer film disposed on an opposite side of the protective film from the oxide film; and a member provided between the oxide film and the protective film in cross-sectional view, wherein the member is disposed to overlap at least a boundary between the first semiconductor region and the third semiconductor region in plan view. Shimada fails to disclose the limitation where a member provided on an opposite side of the oxide film from the semiconductor layer in cross-sectional view; wiring; and a contact plug configured to connect the wiring to the first surface of the semiconductor layer, wherein the member is disposed to overlap at least a boundary between the first semiconductor region and the third semiconductor region in plan view, wherein the member is disposed between the wiring and the semiconductor layer, and wherein a work function of the member differs from a work function of each of the first semiconductor region and the third semiconductor region so that a potential gradient for signal charge is generated in a depth direction of the semiconductor layer at at least the boundary. However, Miyajima eta l. discloses an avalanche photodiode where in paragraphs 0073, 0074, 0076, the required member (n/p doped polysilicon) is disclosed. Furthermore, Kasukawa discloses an avalanche photodiode where in paragraph 0172 along with paragraphs 0125, 0126, 0127, 0153, 0154 and 0255, the required workfunction/potential gradient is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required member and potential gradient in Shimada as taught by Miyajima and Kasukawa, respectively, in order to increase the performance of the avalanche photodiode.
Regarding Claim 12, in Shimada, Miyajima et al. and Kasukawa combination, wherein an interface state density between the oxide film and the member is lower than an interface state density between the oxide film and the protective film.
Regarding Claim 13, in Shimada, Miyajima et al. and Kasukawa combination, wherein an outer edge of the member is disposed within one pixel in plan view.
Regarding Claim 14, in Shimada, Miyajima et al. and Kasukawa combination, further comprising: a first wiring portion electrically connected to the first semiconductor region; and a second wiring portion electrically connected to the second semiconductor region, wherein the first wiring portion is electrically connected to the member.
Regarding Claim 15, in Shimada, Miyajima et al. and Kasukawa combination, wherein the member overlaps the entire first semiconductor region in plan view.
Regarding Claim 16, in Shimada, Miyajima et al. and Kasukawa combination, wherein the member overlaps the entire third semiconductor region in plan view.
Regarding Claim 17, in Fig 7 paragraph 0132 and Fig. 11 paragraph 0146, along with paragraph 0170-183 (SPAD), Shimada et al. discloses a photoelectric conversion apparatus including an avalanche photodiode, the apparatus comprising: a semiconductor layer having a first surface and a second surface; a first semiconductor region of a first conductivity type disposed at a first depth; A second semiconductor region of a second conductivity type disposed at a second depth that is greater than the first depth from the first surface, wherein the second semiconductor region forms the avalanche photodiode together with the first semiconductor region; a third semiconductor region of the first conductivity type provided in contact with an end portion of the first semiconductor region; an oxide film disposed on the first surface of the semiconductor layer; a member provided on an opposite side of the oxide film from the semiconductor layer in cross-sectional view; wiring; and a contact plug configured to connect the wiring to the first surface of the semiconductor layer, wherein the member is disposed to overlap at least a boundary between the first semiconductor region and the third semiconductor region in plan view, wherein the member is disposed between the wiring and the semiconductor layer, and wherein the member is made of second conductivity type polysilicon. Shimada fails to disclose the limitation where a member provided on an opposite side of the oxide film from the semiconductor layer in cross-sectional view; wiring; and a contact plug configured to connect the wiring to the first surface of the semiconductor layer, wherein the member is disposed to overlap at least a boundary between the first semiconductor region and the third semiconductor region in plan view, wherein the member is disposed between the wiring and the semiconductor layer, and wherein a work function of the member differs from a work function of each of the first semiconductor region and the third semiconductor region so that a potential gradient for signal charge is generated in a depth direction of the semiconductor layer at at least the boundary. However, Miyajima eta l. discloses an avalanche photodiode where in paragraphs 0073, 0074, 0076, the required member (n/p doped polysilicon) is disclosed. Furthermore, Kasukawa discloses an avalanche photodiode where in paragraph 0172 along with paragraphs 0125, 0126, 0127, 0153, 0154 and 0255, the required workfunction/potential gradient is disclosed.
It would have been obvious to one of having ordinary skill in the art before the effective filing date of the claimed invention to have the required member and potential gradient in Shimada as taught by Miyajima and Kasukawa, respectively, in order to increase the performance of the avalanche photodiode.
Regarding Claim 18, in Shimada, Miyajima et al. and Kasukawa combination, further comprising: a first wiring portion electrically connected to the first semiconductor region; and a second wiring portion electrically connected to the second semiconductor region, wherein the first wiring portion is electrically connected to the member.
Regarding Claim 19, in Shimada, Miyajima et al. and Kasukawa combination, and a signal processing unit configured to generate an image by using a signal output from the photoelectric conversion apparatus.
Regarding Claim 20, in Shimada, Miyajima et al. and Kasukawa combination, a mobile object comprising: the photoelectric conversion apparatus according to Claim 1; and a control unit configured to control movement of the mobile object by using a signal output from the photoelectric conversion apparatus.
Conclusion
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 1/22/2026