Prosecution Insights
Last updated: April 19, 2026
Application No. 18/523,509

CONTACT STRUCTURE OF SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREFOR

Non-Final OA §102§103
Filed
Nov 29, 2023
Examiner
SLUTSKER, JULIA
Art Unit
2891
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Silicon-Magic Semiconductor Technology (Hangzhou) Co. Ltd.
OA Round
1 (Non-Final)
77%
Grant Probability
Favorable
1-2
OA Rounds
2y 5m
To Grant
90%
With Interview

Examiner Intelligence

Grants 77% — above average
77%
Career Allow Rate
808 granted / 1051 resolved
+8.9% vs TC avg
Moderate +13% lift
Without
With
+12.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
54 currently pending
Career history
1105
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
47.4%
+7.4% vs TC avg
§102
24.8%
-15.2% vs TC avg
§112
20.1%
-19.9% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1051 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1, 2, 4, and 5 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Huang (US 2019/0371898). Regarding claim 1, Huang discloses a contact structure of a semiconductor device, wherein the semiconductor device comprises an epitaxial layer (Fig.9A; Fig.12, numeral 274) and a doped region (292) located in the epitaxial layer (274), and the contact structure comprises: an interlayer dielectric layer (297); (230), arranged on the epitaxial layer (274); a contact hole (236), comprising a first portion (Fig.11, numeral 23n) extending through the interlayer dielectric layer (297); (230) and a second portion (234h) extending into the doped region (292), wherein a size of the first portion is greater than a size of the second portion ([0045]; [0058] note: height 234h is less than the height of upper part of (236n)), the second portion is open on a bottom surface of the first portion (Fig.12), and a bottom surface of the second portion (236h) is arranged in the doped region (292); a contact layer (219), comprising a first contact layer (upper part of (219)) arranged on the bottom surface of the first portion (282t) and a second contact layer (lower part of (219); (214)) arranged on the bottom surface of the second portion (236h); and a conductive channel (236), arranged in the contact hole and contacting the contact layer (219). Regarding claim 2, Huang discloses wherein the first contact layer (219) is an annular structure surrounding the conductive channel (236) (Fig.12), an annular bottom surface and an outer side wall of the first contact layer (219) contact the epitaxial layer (274) (note: claim language does not require “direct physical contact”), and a top surface and an inner side wall of the first contact layer (219) contact the conductive channel (236). Regarding claim 4, Huang discloses wherein a contact area between the conductive channel (Fig.12, numeral 236) and the epitaxial layer (274) is a sum of a contact area between the first contact layer (236n) and the epitaxial layer (274) and a contact area between the second contact layer (236n) and the epitaxial layer (274) ([0059]). Regarding claim 5, Huang discloses wherein the lower surface of the first contact layer (236n) is flush with the upper surface of the second contact layer (236h). Claim(s) 1, 2, 4, 5, 9, 10-12, 14, and 16 are rejected under 35 U.S.C. 102(a)(1)/(a)/(2) as being anticipated by Su (US 2019/0122920). Regarding claim 1, Su discloses a contact structure of a semiconductor device, wherein the semiconductor device comprises an epitaxial layer (Fig.7, numeral 10) and a doped region (26) located in the epitaxial layer (10), and the contact structure comprises: an interlayer dielectric layer (22), arranged on the epitaxial layer (10); a contact hole (50), comprising a first portion (upper part of (50) extending through the interlayer dielectric layer (22) and a second portion (lower part of (50)) extending into the doped region (26), wherein a size of the first portion is greater than a size of the second portion (Figs.7, 8), the second portion is open on a bottom surface of the first portion (Fig.7), and a bottom surface of the second portion is arranged in the doped region (26); a contact layer (38), comprising a first contact layer (upper part of (38)) arranged on the bottom surface of the first portion (50) and a second contact layer (lower part of (38); (42)) arranged on the bottom surface of the second portion (50); and a conductive channel (40), arranged in the contact hole and contacting the contact layer (36). Regarding claim 2, Su discloses wherein the first contact layer (38) is an annular structure surrounding the conductive channel (40), an annular bottom surface and an outer side wall of the first contact layer (38) contact the epitaxial layer (10) (note: claim language does not require “direct physical contact”), and a top surface and an inner side wall of the first contact layer (36) contact the conductive channel (40). Regarding claim 4, Su discloses wherein a contact area between the conductive channel (40) and the epitaxial layer (10) is a sum of a contact area between the first contact layer (38) and the epitaxial layer (10) and a contact area between the second contact layer (38) and the epitaxial layer (10) (Fig.7). Regarding claim 5, Su discloses wherein the lower surface of the first contact layer 38) is flush with the upper surface of the second contact layer (lower part of (38); (42)). Regarding claim 9, Su discloses wherein the contact structure further comprises a side surface connected to the bottom surface of the first portion and the bottom surface of the second portion, the side surface is inclined relative to the bottom surface of the first portion and the bottom surface of the second portion, and a size of a top of the second portion is greater than a size of a bottom of the second portion (Fig.12). Regarding claim 10, Su discloses wherein the contact layer (38) further comprises a fourth contact layer covering the side surface, a top end of the fourth contact layer contacts the first contact layer, and a bottom end contacts the second contact layer ([0022]; note (38) is a multilayer). Regarding claim 11, Su discloses a manufacturing method for manufacturing a contact structure of a semiconductor device, wherein the semiconductor device comprises an epitaxial layer (Fig.7, numeral 14; [0017]) and a doped region (26) located in the epitaxial layer (14), and the manufacturing method comprises: forming an interlayer dielectric layer (22) on the epitaxial layer (24); forming a contact hole (36), wherein the contact hole comprises a first portion extending through the interlayer dielectric layer (22) and a second portion extending into the doped region (26), a size of the first portion is greater than a size of the second portion, the second portion is open on a bottom surface of the first portion (Figs. 7, 8), and a bottom surface of the second portion is arranged in the doped region (26); forming a contact layer (38), wherein the contact layer comprises a first contact layer (upper part of (38) arranged on the bottom surface of the first portion and a second contact layer (lower part of (38); (42) arranged on the bottom surface of the second portion; and forming a conductive channel (40) filling the contact hole (36) and contacting the contact layer (38). Regarding claim 12, Su discloses forming a contact hole (36) extending through the interlayer dielectric layer (22) to an inside of the epitaxial layer (14), wherein the contact hole comprises a first portion extending through the interlayer dielectric layer (22) and a second portion extending into the doped region (26), the second portion is open on a bottom surface of the first portion, and a bottom surface of the second portion is arranged in the doped region (26); and selectively etching a side wall of the first portion of the contact hole, so that the size of the first portion is greater than the size of the second portion (Fig.6; [0020]; [0021]). Regarding claim 14, Su discloses wherein the first contact layer (38) is an annular structure surrounding the conductive channel, an annular bottom surface and an outer side wall of the first contact layer contact the epitaxial layer, and a top surface and an inner side wall of the first contact layer contact the conductive channel (Figs. 7, 8). Regarding claim 16, Su discloses the lower surface of the first contact layer (upper part (38) is flush with the upper surface of the second contact layer (lower part of (38); Fig. 7). Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Huang as applied to claim 1 above, and further in view of Park (US 2016/0351570). Regarding claim 3, Huang discloses, a bottom surface and a side wall of the second contact layer (219) contact the epitaxial layer (274), and a top surface of the second contact layer (210) contacts the conductive channel (236). Huang does not disclose wherein the second contact layer is a pillar structure. Park however discloses the second contact layer (284) is a pillar structure (Fig.19B). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Huang with Park to have the second contact layer as a pillar structure for the purpose of forming contact plugs (Park; [0049]). Claim(s) 3 and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 1 and 11 above, and further in view of Park (US 2016/0351570). Regarding claim 3, Su discloses, a bottom surface and a side wall of the second contact layer (38) contact the epitaxial layer (14), and a top surface of the second contact layer (28) contacts the conductive channel (40). Su does not disclose wherein the second contact layer is a pillar structure. Park however discloses the second contact layer (284) is a pillar structure (Fig.19B). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was filed to modify Su with Park to have the second contact layer as a pillar structure for the purpose of forming contact plugs (Park; [0049]). Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Su as applied to claim 11 above, and further in view of Huang’190 (US 2021/0091190). Regarding claim 13, Su does not disclose wherein a side wall of the second portion of the contact hole is selectively etched through wet etching. Huang’190 however discloses wherein a side wall of the second portion of the contact hole is selectively etched through wet etching ([0040]). It would have been therefore obvious to one of ordinary skill in the art at the time the invention was field to modify Su with Huang’190 to have a side wall of the second portion of the contact hole is selectively etched through wet etching because wet etching is one of typical methods for forming contact holes. Allowable Subject Matter Claims 6-8 and 17-21 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the search of the prior art does not disclose or reasonably suggest wherein the second portion of the contact hole further comprises a plurality of levels of second contact holes of different sizes, the second contact hole of each level is open on a bottom surface of the second contact hole of a previous level, and sizes of the plurality of levels of second contact holes successively decrease from top to bottom as required by claims 6 and 17. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JULIA SLUTSKER whose telephone number is (571)270-3849. The examiner can normally be reached Monday-Friday, 9 am-6 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Matthew Landau can be reached at 571-272-1731. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JULIA SLUTSKER/Primary Examiner, Art Unit 2891
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Prosecution Timeline

Nov 29, 2023
Application Filed
Jan 23, 2026
Non-Final Rejection — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
77%
Grant Probability
90%
With Interview (+12.6%)
2y 5m
Median Time to Grant
Low
PTA Risk
Based on 1051 resolved cases by this examiner. Grant probability derived from career allow rate.

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