DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s response filed on 09/11/2025 in which claims 1-7, 9-13, 15-19 are pending has been entered of record.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9-13, and 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Gomm (US Pat. 10,373,671) in view Bulzacchelli et al. (US Pub. 2012/0314721).
Regarding claim 1, Fig. 1 of Gomm discloses an electronic device, comprising:
a clock input buffer [18] configured to receive a clock signal [clk_t];
a jitter generator [48] coupled to the clock input buffer [18], wherein the jitter generator is configured to generate a jittered clock signal [output of 48] based on receiving a clock signal [CLK];
control circuitry [combination of 32 and 30] coupled to the jitter generator [48], wherein the control circuitry is configured to generate output data based on receiving input data [data from COMMAND INTERFACE 14] and the jittered clock signal [output of 48]; and
input/output circuit [16] configured to provide output data [DQ] to one or more external devices responsive to the clock signal [output of 48].
Gomm does not specially disclose a multiplexer coupled to the clock input buffer, the jitter generator, and the input/output circuit, wherein the multiplexer is configured to selectively provide the clock signal or the jittered clock signal to the input/output circuit. However, Fig. 2 of Bulzacchelli discloses a memory device having multiple clock signals [CLK_A, CLK_B] connects to a multiplexer [232], wherein the multiplexer [232] is configured to selectively provide one of the clock signal to the input/output circuit [240].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Bulzacchelli’s memory device having multiplexer such that Gomm memory device able to select one of the two clocks according to Bulzacchelli’s teachings for the purpose of selecting a more suitable clock signal for each memory operation.
Regarding claim 2, Fig. 1 of Gomm discloses wherein the input/output circuit [16] provide the output data [DQ] by latching the output data with the jittered clock signal [output from 48].
Regarding claim 3, Fig. 1 of Gomm discloses wherein the jittered clock signal [output of 48] is configured to comprise the clock signal having induced jitter thereon [as shows in Fig. 4A and 4B].
Regarding claim 4, Fig. 4A and Fig. 4B of Gomm discloses wherein the jittered clock signal is configured to have a jittering frequency within a frequency range [can be any range].
Regarding claim 5, fig. 4B of Gomm discloses wherein the frequency range comprises a frequency of the clock signal [CLK at 400ps].
Regarding claim 6, Fig. 1 of Gomm discloses wherein the control circuitry comprises a memory device comprising one or more memory banks [more than 3 banks 12].
Regarding claim 7, Fig. 1 of Gomm discloses wherein the one or more memory banks are configured to receive the input data [DQ or ZQ] and provide the output data based on receiving the jittered clock signal [output of 48].
Regarding claims 9 and 15, Fig. 1 of Gomm discloses wherein the input/output circuit [16] provide the output data [DQ] by latching the output data based on receiving the clock signal or the jittered clock signal [output of 48].
Regarding claim 10, Fig. 1 of Gomm discloses a memory device, comprising:
one or more memory banks [12] configured to store and retrieve data;
a jitter generator [48] configured to provide a jittered clock signal [output of 48] based on receiving a clock signal [CLK];
an input/output interface [16] configured to receive input data [DQ or ZQ] and provide output data [DQ];
a command decoder [32] coupled to the one or more memory banks [12], the jitter generator [48], and the input/output interface [16], wherein the command decoder is configured to provide access instructions [output of 32] to the one or more memory banks [12] to store or retrieve the data based on receiving the input data and the jittered clock signal [output of 48].
Gomm does not specially disclose a multiplexer coupled to the clock input buffer, the jitter generator, and the input/output circuit, wherein the multiplexer is configured to selectively provide the clock signal or the jittered clock signal to the input/output circuit. However, Fig. 2 of Bulzacchelli discloses a memory device having multiple clock signals [CLK_A, CLK_B] connects to a multiplexer [232], wherein the multiplexer [232] is configured to selectively provide one of the clock signal to the input/output circuit [240].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Bulzacchelli’s memory device having multiplexer such that Gomm memory device able to select one of the two clocks according to Bulzacchelli’s teachings for the purpose of selecting a more suitable clock signal for each memory operation.
Regarding claim 11, Fig. 1 of Gomm discloses wherein the command decoder [32] is configured to provide the output data [any data from 32] based on receiving the jittered clock signal [output of 48].
Regarding claims 12 and 18, Fig. 8A of Gomm discloses wherein a frequency of the jittered clock signal comprises a frequency of the clock signal [as shows in Fig. 8B] having positively and negatively induced frequency jitter values [col. 4, line 36 to 52].
Regarding claims 13 and 19, Fig. 4B of Gomm discloses wherein the jittered clock signal is configured to have a jittering frequency within a frequency range [can be any range], wherein the frequency range comprises a frequency of the clock signal [CLK at 400ps].
Regarding claim 16, Fig. 1 of Gomm discloses a memory system comprising:
a registering clock driver [18] configured to provide a clock signal [CLK] having a core clock frequency;
a plurality of memory devices [12] coupled to the registering clock driver [18], wherein the memory devices each comprise:
one or more respective memory banks [12] configured to store and retrieve data [inherently for memory array];
a respective jitter generator [48] configured to provide a respective jittered clock signal [output of 48] based on receiving the clock signal [CLK];
a respective input/output interface [16] configured to receive input data [DQ OR ZQ] and provide output data [DQ]; and
a respective command decoder [32] coupled to the one or more respective memory banks [12], the respective jitter generator [48], and the respective input/output interface [16].
Gomm does not specially disclose a multiplexer coupled to the clock input buffer, the jitter generator, and the input/output circuit, wherein the multiplexer is configured to selectively provide the clock signal or the jittered clock signal to the input/output circuit. However, Fig. 2 of Bulzacchelli discloses a memory device having multiple clock signals [CLK_A, CLK_B] connects to a multiplexer [232], wherein the multiplexer [232] is configured to selectively provide one of the clock signal to the input/output circuit [240].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Bulzacchelli’s memory device having multiplexer such that Gomm memory device able to select one of the two clocks according to Bulzacchelli’s teachings for the purpose of selecting a more suitable clock signal for each memory operation.
Regarding claim 17, Fig. 1 of Gomm discloses wherein the respective command decoder [32] is configured to provide access instructions to the one or more respective memory banks [12] to store or retrieve the data based on receiving the input data and the respective jittered clock signal [output of 48] and provide the output data based on receiving the respective jittered clock signal [output of 48].
Response to Arguments
Applicant's arguments filed 09/11/2025 have been fully considered but they are not persuasive.
Applicant argues that Gomm in view Bulzacchelli does not teach or suggest “a multiplexer coupled to the clock input buffer, the jitter generator, and the input/output circuit, wherein the multiplexer is configured to selectively provide the clock signal or the jittered clock signal to the input/output circuit”. Applicant is reminded that the claims are examined in light of broadest reasonable interpretation. Also, although the claims are examined in light of specification, limitations from specifications are not read into the claims. See MPEP 2100.
As discloses in col. 1 lines 29 to 60, electrical signals may degrade over time due to clock variable. Therefore, jittering clock signal will improve the electrical signals. As discloses in Col. 8, line 41 to col. 9, line 4, the combination of controller 14 and jitter generator [48] will output either a jittered clock signal [output of 48] or pass-through clean clock signal [CLK] to the interface 16 for some memory operations. Therefore, similar to the application, Gomn teaches either applies clean clock signal [CLK] or jittered clock signal to the interface. Gomn able to apply one of the clock signal without showing a multiplexer. However, the idea of using a multiplexer to select one of a clock signal is well known in the art, which shows by Bulzacchelli in Fig. 2. Therefore, it is obvious to an ordinary skill in the art at the time of the invention was made to use a multiplexer to select one of a clock signal more affectively.
Therefore, all applicant’s arguments were fully considered, they are not persuasive.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825
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