DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species A, claims 1-20 in the reply filed on 04/02/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/29/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the "second side surface has Y second internal laser etching patterns arranged horizontally" must be shown or the feature canceled from the claim. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 2, 6, 7, 10, and 16 are rejected under 35 U.S.C. 102 as being anticipated by Ting et al. ( US 2016/0247964 A1; hereinafter Ting )
Regarding claim 1, Ting teaches a manufacturing method of a light-emitting diode ( [0028] Referring to FIG. 5, each of the LEDs 20 manufactured using the manufacturing method of the disclosure and the LED wafer 2 in FIG. 1 ), comprising: providing an LED wafer ( Fig. 1 wafer 2 ), wherein the LED wafer comprises a substrate ( Fig. 1 substrate 21 ) and a light-emitting semiconductor stacking structure ( Fig. 1 light-emitting unit 22 ) positioned on an upper surface of the substrate ( Fig. 1 #21 ), the light-emitting semiconductor stacking structure ( Fig. 1 #22 ) comprises a first type semiconductor layer ( Fig. 1 n-type semiconductor layer 221 ), an active layer ( Fig. 1 light-emitting layer 223 ), and a second type semiconductor layer ( Fig. 1 p-type semiconductor layer 222 ) from a side of the substrate ( Fig. 1 #21 ); defining dicing lanes on an upper surface of the LED wafer ( [0026] Step 16: the LED wafer 2 together with the fixing piece 4 are cut and broken, such that the LED wafer 2 forms a plurality of LEDs 20. Specifically, the LED wafer 2 is cut into a plurality of blocks by way of laser scribing according to a predetermined size ); dicing is performed along the dicing lanes of the substrate using a laser ( as discussed above ): focusing the laser on a lower surface of the substrate to form a surface hole, and focusing the laser inside the substrate to form an internal hole, wherein a diameter of the surface hole is greater than a diameter of the internal hole, the diameter of the surface hole is 5 to 15 µm, and the diameter of the internal hole is 3 to 5 µm ( Stealth Dicing is an inherent process as described in Kiyota et al., “Numerical simulation and validation of subsurface modification and crack formation induced by nanosecond-pulsed laser processing in monocrystalline silicon,” J. Appl. Phys. 127. 085106 (2020)); and separating the LED wafer into a plurality of LED chips along the dicing lanes ( as discussed above).
Regarding claim 2, Ting teaches the manufacturing method of the light-emitting diode as claimed in claim 1 ( as discussed above), wherein a depth of the surface hole is 1/10 to 1/5 of a thickness of the substrate ( inherent to the Stealth Dicing method described in Kiyota (2020) and shown in Fig. 5 ).
Regarding claim 6, Ting teaches the manufacturing method of the light-emitting diode as claimed in claim 1 ( as discussed above ) wherein in the LED chip formed in the manufacturing method ( [0020] The substrate 21 has a thickness around 430 μm, and has a first side 211 and a second side 212 opposite to the first side 211 ), an angle between a side wall of the substrate and the upper surface of the substrate is 85 to 95 ( as shown in Fig. 1 the angle between the side wall of the substrate and the upper surface of the substrate is 90 degrees ).
Regarding claim 7, Ting teaches the manufacturing method of the light-emitting diode as claimed in claim 1 ( as discussed above ), wherein a thickness of the substrate is greater than or equal to 80 µm and less than or equal to 200 µm, or greater than 200 µm and less than or equal to 750 µm ( [0020] The substrate 21 has a thickness around 430 μm, and has a first side 211 and a second side 212 opposite to the first side 211 ).
Regarding claim 10, Ting teaches a light-emitting diode ( ), comprising a substrate ( Fig. 1 substrate 21 ) and a light-emitting semiconductor stacking structure ( Fig. 1 light-emitting unit 22 ) positioned on an upper surface ( as shown in Fig. 1 ) of the substrate ( Fig. 1 #21 ), wherein the light-emitting semiconductor stacking structure ( Fig. 1 #22 ) comprises a first type semiconductor layer ( Fig. 1 n-type semiconductor layer 221 ), an active layer ( Fig. 1 light-emitting layer 223 ), and a second type semiconductor layer ( Fig. 1 p-type semiconductor layer 222 ) from a side of the substrate ( Fig. 1 #21 ), at least one side surface of the substrate ( Fig. 1 #21 ) comprises a surface laser etching pattern and an internal laser etching pattern ( an inherent process of Stealth Dicing ), the surface laser etching pattern is a series of recesses extending from a lower surface of the substrate to the upper surface ( as shown in Kiyota Fig. 7 orientation of the wafer in the laser shows exposure from both sides ), the internal laser etching pattern comprises a series of explosion spots formed by laser etching ( as described in the Stealth Dicing process ), diameters of the recesses perpendicular to a thickness direction are greater than diameters of the explosion spots perpendicular to the thickness direction ( as discussed in Kiyota where Stealth Dicing is implemented ), the light-emitting diode is formed by separating an LED wafer along dicing lanes ( [0026] Step 16: the LED wafer 2 together with the fixing piece 4 are cut and broken, such that the LED wafer 2 forms a plurality of LEDs 20. Specifically, the LED wafer 2 is cut into a plurality of blocks by way of laser scribing according to a predetermined size ), the dicing lanes are distributed with a series of surface holes ( as described in the Stealth Dicing process ), the recesses are formed in response to the LED wafer being separated to form the light-emitting diode ( as discussed above in paragraph [0026] ), and diameters of the surface holes are 5 to 15µm ( as described in the Stealth Dicing process by Kiyota).
Regarding claim 16, Ting teaches the light-emitting diode as claimed in claim 10 ( as discussed above ) wherein an angle between a side surface of the substrate and the upper surface of the substrate is 85 to 95 ( as shown in Fig. 1 the angle between the side wall of the substrate and the upper surface of the substrate is 90 degrees ).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 15 are rejected under U.S.C. 103 as being unpatentable over Ting et al.; US 2016/0247964 A1; 02/2016 in view of Hooper et al.; US 2011/0298156 A1; 03/2011
Claim 3: Ting discloses the manufacturing method of the light-emitting diode as claimed in claim 1 ( as discussed above).
Ting does not appear to disclose the dicing lanes defined in the second step comprise a first direction and a second direction, the first direction is perpendicular to the second direction, wherein in the third step, X scribe lines are formed on same cross-section inside the substrate along the first direction using a first laser beam, and Y scribe lines are formed on same cross-section inside the substrate along the second direction using a second laser beam, wherein a pulse energy of the first laser beam is greater than a pulse energy of the second laser beam.
However, Hooper(‘156) teaches the dicing lanes ( Figs. 9B, 9C, and 9D ) defined in the second step comprise a first direction ( Fig. 8 shows X direction for the wafer 810 ) and a second direction ( Fig 8 shows Y direction for wafer 810 ), the first direction is perpendicular to the second direction ( as shown in Fig. 8 ), wherein in the third step, X scribe lines ( Fig. 9B ) are formed on same cross-section inside the substrate ( Fig, 10 substrate 1014 ) along the first direction using a first laser beam ( Fig. 9B temporal pulse profile 918 ), and Y scribe lines ( Fig. 9C ) are formed on same cross-section inside the substrate ( Fig. 10 #1014 ) along the second direction using a second laser beam ( Fig. 9C temporal pulse profile 920 ), wherein a pulse energy of the first laser beam ( as shown in Fig. 9B ) is greater than a pulse energy of the second laser beam ( as shown in Fig. 9C ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hooper(‘156) with Ting to implement the dicing lanes defined in the second step comprise a first direction and a second direction, the first direction is perpendicular to the second direction, wherein in the third step, X scribe lines are formed on same cross-section inside the substrate along the first direction using a first laser beam, and Y scribe lines are formed on same cross-section inside the substrate along the second direction using a second laser beam, wherein a pulse energy of the first laser beam is greater than a pulse energy of the second laser beam because the two step process is used to scribe then break the sections of the wafer for separation.
Claim 15: Ting discloses the light-emitting diode as claimed in claim 10 (as discussed above ).
Ting does not appear to disclose a spacing is between the internal laser etching pattern and the surface laser etching pattern.
However, Hooper teaches a spacing is between the internal laser etching pattern ( Fig. 10 step 2 – cut through substrate ) and the surface laser etching pattern ( Fig. 10 step 1 – scribe circuitry layer ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Hooper(‘156) with Ting to implement a spacing is between the internal laser etching pattern and the surface laser etching pattern because this approach ensures precise and controlled crack propagation for reliable die separation.
Claims 4 and 5 are rejected under U.S.C. 103 as being unpatentable over Ting et al.; US 2016/0247964 A1; 02/2016 in view of Hooper et al.; US 2011/0298156 A1; 03/2011 as it relates to claim 3 above and further in view of Lapke et al. ; US 2019/0080963 A1; 09/2017
Claim 4: Ting and Hooper(‘156) disclose the manufacturing method of the light-emitting diode as claimed in claim 3 ( as discussed above ).
Neither Ting nor Hooper(‘156 ) appear to disclose 1≤X≤5.
However, Lapke teaches 1≤X≤5 ( Fig. 3 cutting lanes 306(1)-(M)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lapke with Ting and Hooper (‘156 ) to implement 1≤X≤5 because this range maximizes density and wafer yield while providing balance between wafer fragility and operational safety during dicing.
Claim 5: Ting, Hooper(‘156), and Lapke disclose the manufacturing method of the light-emitting diode as claimed in claim 3 ( as discussed above ).
Neither Ting nor Hooper(‘156) appear to disclose 2≤Y≤20.
However, Lapke teaches 2≤Y≤20 ( Fig. 3 cutting lanes 308(1)-(N)).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lapke with Ting and Hooper(‘156) to implement 2≤Y≤20 because this distance balances mechanical support, cleaving efficiency, die protection, and yield optimization.
Claims 8-9, 11-14, and 20 are rejected under U.S.C. 103 as being unpatentable over Ting et al.; US 2016/0247964 A1; 02/2016 in view of Kiyota et al., “Numerical simulation and validation of subsurface modification and crack formation induced by nanosecond-pulsed laser processing in monocrystalline silicon,” J. Appl. Phys. 127. 085106 (2020)
Claim 8: Ting discloses the manufacturing method of the light-emitting diode as claimed in claim 1 ( as discussed above ).
Ting does not appear to disclose a distance between the internal hole and the upper surface of the substrate is greater than or equal to 10 µm.
However, Kiyota teaches a distance between the internal hole and the upper surface of the substrate is greater than or equal to 10 µm ( Fig. 4 internal hole and upper surface distance is greater than 10 µm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kiyota with Ting to implement a distance between the internal hole and the upper surface of the substrate is greater than or equal to 10 µm because the distance enhances light extraction efficiency, provides mechanical clearance, and facilitates thermal management.
Claim 9: Ting discloses the manufacturing method of the light-emitting diode as claimed in claim 1 ( as discussed above ).
Ting does not appear to disclose a spacing is between the surface hole and the internal hole.
However, Kiyota teaches a spacing is between the surface hole and the internal hole ( as shown in Fig. 1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kiyota with Ting to implement a spacing is between the surface hole and the internal hole because the spacing is carefully engineered to balance drilling tolerance, plating quality, long-term reliability.
Claim 11: Ting discloses the light-emitting diode as claimed in claim 10 ( as discussed above).
Ting does not appear to disclose the at least one side surface comprises a crack connected to the internal laser etching pattern, and the crack extends toward the upper surface and the lower surface of the substrate.
However, Kiyota teaches the at least one side surface comprises a crack connected to the internal laser etching pattern ( page 127 section B lines 2-4 The laser induced structures, i.e., the void, the disordered region, and the crack are clearly observed with this non-destructive method ), and the crack extends toward the upper surface and the lower surface of the substrate ( as shown in Fig. 11 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kiyota with Ting to implement the at least one side surface comprises a crack connected to the internal laser etching pattern, and the crack extends toward the upper surface and the lower surface of the substrate because these are dicing channels that are used to separate the devices during the dicing process.
Claim 12: Ting and Kiyota disclose the light-emitting diode as claimed in claim 11 ( as discussed above ).
Ting does not appear to disclose a portion of the crack extends toward the lower surface of the substrate and ends at the surface laser etching pattern.
However, Kiyota teaches a portion of the crack extends toward the lower surface of the substrate ( as shown in Fig. 11 ) and ends at the surface laser etching pattern ( Fig. 11 crack ends at void )
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kiyota with Ting to implement a portion of the crack extends toward the lower surface of the substrate and ends at the surface laser etching pattern because the channel crack is part of the dicing process.
Claim 13: Ting and Kiyota disclose the light-emitting diode as claimed in claim 11 ( as discussed above ).
Ting discloses a horizontal crack positioned between the two columns of internal laser etching patterns ( [0026] by applying an instant impact on the LED wafer 2 along the trace of the cutting line ).
Ting does not appear to disclose the at least one side surface comprises at least two columns of internal laser etching patterns.
However, Kiyota teaches the at least one side surface comprises at least two columns of internal laser etching patterns ( as shown in Fig. 10 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kiyota with Ting to implement the at least one side surface comprises at least two columns of internal laser etching patterns because this approach enhances epitaxial growth uniformity and improves manufacturing yield.
Claim 14: Ting discloses the light-emitting diode as claimed in claim 10 ( as discussed above).
Ting does not appear to disclose a depth of the surface laser etching pattern is 1/10 to 1/5 of a thickness of the substrate.
However, Kiyota teaches a depth of the surface laser etching pattern is 1/10 to 1/5 of a thickness of the substrate ( as shown in Fig. 5 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kiyota with Ting to implement a depth of the surface laser etching pattern is 1/10 to 1/5 of a thickness of the substrate because this range allows controlled stress-induced die separation yet it is shallow enough to protect the active device layers.
Claim 20: Ting discloses the light-emitting diode as claimed in claim 10 ( as discussed above).
Ting does not appear to disclose a distance between the internal laser etching pattern and the upper surface of the substrate is greater than or equal to 10 µm.
However, Kiyota teaches a distance between the laser etching pattern and the upper surface of the substrate is greater than or equal to 10 µm ( Fig. 4 internal laser etching pattern and upper surface distance is greater than 10 µm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kiyota with Ting to implement a distance between the internal laser etching pattern and the upper surface of the substrate is greater than or equal to 10 µm because this approach is used to control internal stress distribution, prevent unintended microcracking, and maximize device yield.
Claim 17 is rejected under U.S.C. 103 as being unpatentable over Ting et al.; US 2016/0247964 A1; 02/2016 in view of Song; US 12,074,267 B2; 11/2019
Claim 17: Ting discloses the light-emitting diode as claimed in claim 10 ( as discussed above).
Ting does not appear to disclose a side length of at least one edge of the upper surface of the substrate is of 200 to 300 µm, 100 to 200 µm, or 40 to 100 µm.
However, Song teaches a side length of at least one edge of the upper surface of the substrate is of 200 to 300 µm, 100 to 200 µm, or 40 to 100 µm (Col 9 lines 20-25 The size of the individual semiconductor light emitting device 150 may be less than 80 μm in the length of one side thereof, and formed with a rectangular or square shaped element. In case of a rectangular shaped element, the size thereof may be less than 20×80 μm ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Kiyota with Song to implement a side length of at least one edge of the upper surface of the substrate is of 200 to 300 µm, 100 to 200 µm, or 40 to 100 µm because these lengths ensure sufficient bonding area and safe placement of vias and metallization without edge cracks.
Claim 18 is rejected under U.S.C. 103 as being unpatentable over Ting et al.; US 2016/0247964 A1; 02/2016 in view of Lapke et al. ; US 2019/0080963 A1; 09/2017
Claim 18: Ting discloses the light-emitting diode as claimed in claim 10 ( as discussed above ).
Ting does not appear to disclose the substrate comprises a first side surface and a second side surface adjacent to each other, the first side surface has X first internal laser etching patterns arranged horizontally, and the second side surface has Y second internal laser etching patterns arranged horizontally, wherein Y > X >0, and Y>2.
However, Lapke teaches the substrate comprises a first side surface ( Fig. 3 cutting lanes 306(1)-(M)) and a second side surface ( Fig. 3 cutting lanes 308(1)-(N) )adjacent to each other, the first side surface has X first internal laser etching patterns arranged horizontally ( as shown in Fig. 3 ), and the second side surface has Y second internal laser etching patterns arranged horizontally ( as shown in Fig. 3 arranged vertically ), wherein Y > X >0, and Y>2 ( as shown in Fig. 3 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Lapke with Ting to implement the substrate comprises a first side surface and a second side surface adjacent to each other, the first side surface has X first internal laser etching patterns arranged horizontally, and the second side surface has Y second internal laser etching patterns arranged horizontally, wherein Y > X >0, and Y>2 because this approach controls stress during dicing
Claim 19 is rejected under U.S.C. 103 as being unpatentable over Ting et al.; US 2016/0247964 A1; 02/2016 in view of Lapke et al. ; US 2019/0080963 A1; 09/2017 as it relates to claim 18 and further in view of Fornaroli et al. ; “Dicing of thin SI wafers with a picosecond laser ablation process,” Lasers in Manufacturing Conference (2013) 603-609.
Claim 19: Ting and Lapke disclose the light-emitting diode as claimed in claim 18 ( as discussed above).
Neither Ting nor Lapke appear to disclose a roughness of the first internal laser etching pattern is greater than a roughness of the second internal laser etching pattern.
However, Fornaroli teaches a roughness of the first internal laser etching pattern is greater than a roughness of the second internal laser etching pattern ( Page 608 lines 2-3 A very rough structure with deep pits can be observed after 250 repeats and remains until 1000 repeats ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Fornaroli with Ting and Lapke to implement a roughness of the first internal laser etching pattern is greater than a roughness of the second internal laser etching pattern because the first passes in the dicing process with a laser is rougher than the second passes.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KIMBERLY N FREY whose telephone number is (571)272-5068. The examiner can normally be reached Monday - Friday 7:30 am - 5 pm.
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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