DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I invention, claims 1-10, in the reply filed on March 11, 2026, is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2 and 7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Motomi (JP 2007258617 A) [English Translation PDF].
Regarding claims 1-2, Motomi [English Translation PDF] [Figs.1-6] discloses a semiconductor device comprising:
a semiconductor substrate [57] of a first conductivity type [n-type] having an upper surface and a lower surface;
a pair of first trenches [52] formed in the semiconductor substrate on an upper surface side of the semiconductor substrate and extending in a first direction in plan view;
a pair of first gate insulating films [59] formed inside the pair of first trenches;
a pair of first gate electrodes [60] embedded in the pair of first trenches via the pair of first gate insulating films;
a base region [58] of a second conductivity type [p-type] opposite to the first conductivity type, the base region being formed in the semiconductor substrate on an upper surface side of the semiconductor substrate [Fig.3(a)]; and
a first impurity region [2-2] of the first conductivity type and a second impurity region [2-1] of the first conductivity type formed in the semiconductor substrate on an upper surface side of the semiconductor substrate [Fig.3(c)],
wherein the semiconductor substrate has, between the pair of first trenches [52], a first emitter formation region [2-2; A---A region; Fig.1] and a second emitter formation region [lower region 2-2] that are separated from each other in the first direction, and a separation region [2-1; B---B region; Fig.1] located between the first emitter formation region and the second emitter formation region,
wherein the base region [58] is formed in the semiconductor substrate of each of the first emitter formation region, the second emitter formation region, and the separation region [Figs.1,3],
wherein the first impurity region [2-2] is formed in the base region [58] of each of the first emitter formation region and the second emitter formation region,
wherein the second impurity region [2-1] is formed in the base region [58] at a first location in the separation region, the first location being in contact with the pair of first trenches [52] [Figs.1(a),1(c),3(c)] and
wherein the second impurity region [2-1] is connected to the first impurity region [2-2] of each of the first emitter formation region and the second emitter formation region [Fig.1(a)];
wherein the first impurity region [51] and the second impurity region [51] have the same impurity concentration [Fig.6] [Page 2, lines 4-5; page 5, lines 26-28].
Regarding claim 7, Motomi [English Translation PDF] [Figs.1-6] discloses a semiconductor device comprising:
a semiconductor substrate [57] of a first conductivity type having an upper surface and a lower surface;
a pair of first trenches [52] formed in the semiconductor substrate on an upper surface side of the semiconductor substrate and extending in a first direction in plan view;
a pair of first gate insulating films [59] formed inside the pair of first trenches;
a pair of first gate electrodes [60] embedded in the pair of first trenches via the pair of first gate insulating films;
a base region [58] of a second conductivity type opposite to the first conductivity type, the base region being formed in the semiconductor substrate on an upper surface side of the semiconductor substrate; and
a first impurity region [2-2] of the first conductivity type and a second impurity region [2-1] of the first conductivity type formed in the semiconductor substrate on an upper surface side of the semiconductor substrate,
wherein the semiconductor substrate has, between the pair of first trenches [52], a first emitter formation region [2-2; A---A region; Fig.1] and a second emitter formation region [lower region 2-2] that are separated from each other in the first direction, and a separation region [2-1; B---B region; Fig.1] located between the first emitter formation region and the second emitter formation region,
wherein the base region [58] is formed in the semiconductor substrate of each of the first emitter formation region, the second emitter formation region, and the separation region [Figs.1,3],
wherein the first impurity region [2-2] is formed in the base region of each of the first emitter formation region and the second emitter formation region, and
wherein an impurity concentration of the base region at a first location in contact with the pair of first trenches in the separation region [portions of 58 below 2-1; Fig.1(b)] is lower than an impurity concentration of the base region of each of the first emitter formation region and the second emitter formation region [Portions 3 of 58 below 2-2; Fig.1(c)].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 is/are rejected under 35 U.S.C. 103 as being unpatentable over Motomi (JP 2007258617 A) [English Translation PDF].
Regarding claim 3, Motomi fails to explicitly disclose wherein the first impurity region has an impurity concentration higher than an impurity concentration of the second impurity region. However, Motomi [Page 5, lines 26-31] discloses the impurity concentration of the impurity region 2 can be predetermined and controlled where the impurity concentration of regions 2-2 and 2-1 are different [Fig.1] or are the same [Fig.6]. It would have been obvious to provide wherein the first impurity region has an impurity concentration higher than an impurity concentration of the second impurity region, since it has been held that applying a known technique to a known process in order to yield predictable results would have been obvious. Further, it would have been obvious to try one of the known methods with a reasonable expectation of success. KSR International Co. v. Teleflex Inc., 82 USPQ2d 1385 (2007).
Allowable Subject Matter
Claims 4-6 and 8-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Prior art does not fairly disclose or make obvious the claimed device/method taken as a whole, and specifically, the limitations of
[Claim 4] wherein the second impurity region is formed in the entire base region of the separation region, and wherein an impurity concentration of the second impurity region is 1 x 10¹²/cm³ or more and 1 x 10¹⁴/cm³ or less.
[Claim 5] an interlayer insulating film formed on an upper surface of the semiconductor substrate so as to cover the pair of first trenches;
a hole formed in the interlayer insulating film and the semiconductor substrate so as to penetrate the first impurity region and reach the inside of the base region; and
an emitter electrode formed on the interlayer insulating film,
wherein the base region, the first impurity region, and the second impurity region are electrically connected to the emitter electrode through the hole, and
wherein the second impurity region is physically separated from the hole in the separation region.
[Claim 8] an interlayer insulating film formed on an upper surface of the semiconductor substrate so as to cover the pair of first trenches;
a hole formed in the interlayer insulating film and the semiconductor substrate so as to penetrate the first impurity region and reach the inside of the base region; and
an emitter electrode formed on the interlayer insulating film,
wherein the base region and the first impurity region are electrically connected to the emitter electrode through the hole, and
wherein the base region at the first location is physically separated from the hole.
[Claim 10] wherein an impurity concentration of the entire base region in the separation region is lower than an impurity concentration of the base region of each of the first emitter formation region and the second emitter formation region.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The cited prior art is considered analogous art and discloses at least some of the claimed subject matter of the current invention. However, the prior art does not fairly disclose or make obvious the claimed device/method taken as a whole as provided above.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BAC H AU whose telephone number is (571)272-8795. The examiner can normally be reached M-F 9:00AM-6:00PM.
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/BAC H AU/Primary Examiner, Art Unit 2898