Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in China on 1/31/2023. It is noted, however, an attempt by the Office to electronically retrieve, under the priority document exchange program, the foreign application 202310073190.9 to which priority is claimed has FAILED on 06/30/2024. A certified copy of the CN 202310073190.9 application is required by 37 CFR 1.55.
Prior Art of Record
The applicant's attention is directed to additional pertinent prior art cited in the accompanying PTO-892 Notice of References Cited, which, however, may not be currently applied as a basis for the following rejections. While these references were considered during the examination of this application and are deemed relevant to the claimed subject matter, they are not presently being applied as a basis for rejection in this Office action. The pertinence of these documents, however, may be revisited, and they may be applied in subsequent Office actions, particularly in light of any amendments or further clarification of the claimed invention.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 3, 5, 7, 9-11, 13, 15, 17 and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kang et al. (US 2021/0089158 A1).
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CLAIM 1. Kang teaches an array substrate comprising:
a pixel area comprising a plurality of thin film transistors arranged in a multi-row and multi-column array (Kang discloses an in-cell touch display panel (100) having a display area (101). The display area (101) includes multiple pixel regions (P11-P14, P21-P24, etc.) formed where gate lines intersect data lines, with each pixel structure including a thin film transistor (T1). These TFTs are arranged in rows and columns as shown in Figure 1.); and
a fan-out area comprising a plurality of sub-fan-out areas (A non-display area (102) that includes a fan-out area (104). While Kang describes the fan-out area generally, it inherently contains sub-areas where different groups of signal lines (data and sensing) are routed to respective pads (121-124, 131-134) as shown in Figure 1.),
wherein each of the plurality of sub-fan-out areas is arranged corresponding to a row of the plurality of thin film transistors, and each of the plurality of sub-fan-out areas is connected to a row of thin film transistors corresponding to the corresponding row of thin film transistors by a plurality of M1 traces ( Kang Figure 1 demonstrates gate lines (G1-G4) extending along an X direction (first direction) and data lines (D1-D4) extending along a Y direction (second direction). Kang ¶401 teaches sensing lines (S1-S4) are formed by a first metal layer (M1) in the display area . These M1 lines are electrically connected to the pixel structures (TFTs) in the display area.);
wherein, transverse lengths of a portion of the plurality of M1 traces connected to different thin film transistors in at least one of the plurality of sub-fan-out areas are the same ( Kang illustrates in Figure 1 that the signal lines (sensing and data) are parallel in the display area and remain parallel as they enter the non-display area. In the signal line transferring area (103), the sensing lines (S1/M1/432) [Figure 4 & ¶452] are transferred to another metal layer through a connection structure. Because these traces are routed in parallel to an interleaved pad arrangement (121-124, 131-134), the transverse segments of these M1 traces necessarily have identical lengths to maintain the uniform spacing and parallel alignment described.), and
transverse lengths of another portion of the plurality of M1 traces connected to different thin film transistors in the at least one of the plurality of sub-fan-out areas are different (Kang explicitly shows in Figure 1 that outer fan-out traces must travel a greater horizontal distance to reach pads 121-124 than inner traces, thereby teaching that transverse length of another portion of the M1 traces connected to different thin film transistors are different.); and
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the transverse lengths have a direction same as a distribution direction of a row of the plurality of thin film transistors (Kang's gate lines (defining the rows of TFTs) extend along the X direction. The fan-out traces include segments that align with this X direction to reach the pads.).
CLAIM 3. Kang teaches an array substrate according to claim 1, wherein a portion of the plurality of M1 traces in the at least one of the plurality of sub-fan-out areas span a portion of the plurality of thin film transistors(Kang discloses signal lines (S1-S4, D1-D4) that extend across the display area (101). These traces necessarily span the thin film transistors in the array to provide electrical connectivity across the substrate, as depicted in the array matrix layout of Figure 1.)
CLAIM 5. Kang teaches an array substrate according to claim 1, wherein transverse lengths of a portion of the plurality of M1 traces in each of the plurality of sub-fan-out areas are the same (Kang’s routing architecture is modular. Each group of signal lines (sensing or data) follows a uniform layout pattern. Thus, the transverse lengths of the M1 traces in each respective sub-fan-out area are the same to ensure consistent electrical characteristics across the panel.).
CLAIM 7. Kang teaches an array substrate according to claim 1, wherein the array substrate further comprises a plurality of sensing lines and a plurality of via holes, each of the plurality of sensing lines comprises one or more of transverse sensing lines and one or more of longitudinal sensing lines, each of the plurality of thin film transistors is connected to a portion of the longitudinal sensing lines of each of the plurality of sensing lines , and a portion of the longitudinal sensing lines of each of the plurality of thin film transistors are connected to one or more of the plurality of M1 traces corresponding to the each of the plurality of thin film transistors through respective corresponding via holes (Kang Figures 1 & 4-5 demonstrate sensing lines (S1-S4) comprising transverse and longitudinal segments. Each pixel structure (and its corresponding TFT) is connected to these lines. Kang explicitly describes a connection structure in the signal line transferring area (103) that uses insulation layers and openings (via holes) to connect the M1 traces to other layers.).
CLAIM 9. Kang teaches an array substrate according to claim 1, wherein longitudinal widths of the plurality of M1 traces connected to each of the plurality of thin film transistors are the same (The traces (S1-S4) shown in Kang are illustrated as having uniform width. In the fabrication of array substrates, as taught by Kang, traces in the same metal layer are created with the same longitudinal width to maintain uniform impedance.).
CLAIM 10. Kang teaches an array substrate according to claim 1, wherein longitudinal width of a portion of the plurality of M1 traces in the at least one of the plurality of sub-fan-out areas are the same (As addressed regarding Claim 9, Kang’s M1 traces in the fan-out and transferring areas (103, 104) are uniform. This necessitates that the longitudinal width of the portion of M1 traces in at least one sub-fan-out area is the same.).
CLAIM 11. Kang teaches an display panel comprising an array substrate, wherein the array substrate comprises:
a pixel area comprising a plurality of thin film transistors arranged in a multi-row and multi-column array (Kang discloses an in-cell touch display panel (100) having a display area (101). The display area (101) includes multiple pixel regions (P11-P14, P21-P24, etc.) formed where gate lines intersect data lines, with each pixel structure including a thin film transistor (T1). These TFTs are arranged in rows and columns as shown in Figure 1.); and
a fan-out area comprising a plurality of sub-fan-out areas(A non-display area (102) that includes a fan-out area (104). While Kang describes the fan-out area generally, it inherently contains sub-areas where different groups of signal lines (data and sensing) are routed to respective pads (121-124, 131-134) as shown in Figure 1.),
wherein each of the plurality of sub-fan-out areas is arranged corresponding to a row of the plurality of thin film transistors, and each of the plurality of sub-fan-out areas is connected to a row of thin film transistors corresponding to the corresponding row of thin film transistors by a plurality of M1 traces ( Kang Figure 1 demonstrates gate lines (G1-G4) extending along an X direction (first direction) and data lines (D1-D4) extending along a Y direction (second direction). Kang ¶403 teaches sensing lines (S1-S4) are formed by a first metal layer (M1) in the display area . These M1 lines are electrically connected to the pixel structures (TFTs) in the display area.);
wherein transverse lengths of a portion of the plurality of M1 traces respectively connected to different thin film transistors in at least one of the plurality of sub-fan-out areas are the same( Kang illustrates in Figure 1 that the signal lines (sensing and data) are parallel in the display area and remain parallel as they enter the non-display area. In the signal line transferring area (103), the sensing lines (S1/M1/432) [Figure 4 & ¶454] are transferred to another metal layer through a connection structure. Because these traces are routed in parallel to an interleaved pad arrangement (121-124, 131-134), the transverse segments of these M1 traces necessarily have identical lengths to maintain the uniform spacing and parallel alignment described.), and
transverse lengths of another portion of the plurality of M1 traces connected to different thin film transistors in the at least one of the plurality of sub-fan-out areas are different (Kang explicitly shows in Figure 1 that outer fan-out traces must travel a greater horizontal distance to reach pads 121-124 than inner traces, thereby teaching that transverse length of another portion of the M1 traces connected to different thin film transistors are different.); and
the transverse lengths have a direction same as a distribution direction of a row of the plurality of thin film transistors (Kang's gate lines (defining the rows of TFTs) extend along the X direction. The fan-out traces include segments that align with this X direction to reach the pads.).
CLAIM 13. Kang teaches an display panel according to claim 1, wherein a portion of the plurality of M1 traces in the at least one of the plurality of sub-fan-out areas span a portion of the plurality of thin film transistors (Kang discloses signal lines (S1-S4, D1-D4) that extend across the display area (101). These traces necessarily span the thin film transistors in the array to provide electrical connectivity across the substrate, as depicted in the array matrix layout of Figure 1.)
CLAIM 15. Kang teaches an display panel according to claim 1, wherein transverse lengths of a portion of the plurality of M1 traces in each of the plurality of sub-fan-out areas are the same (Kang’s routing architecture is modular. Each group of signal lines (sensing or data) follows a uniform layout pattern. Thus, the transverse lengths of the M1 traces in each respective sub-fan-out area are the same to ensure consistent electrical characteristics across the panel.).
standardized, parallel manner. By design, these traces have the same transverse lengths to accommodate the standardized distance between the active array and the terminal pads.).
CLAIM 17. Kang teaches an display panel according to claim 1, wherein the array substrate further comprises a plurality of sensing lines and a plurality of via holes，each of the plurality of sensing lines comprises one or more of transverse sensing lines and one or more of longitudinal sensing lines, each of the plurality of thin film transistors is connected to a portion of the longitudinal sensing lines of each of the plurality of sensing lines , and a portion of the longitudinal sensing lines of each of the plurality of thin film transistors are connected to one or more of the plurality of M1 traces corresponding to the each of the plurality of thin film transistors through respective corresponding via holes (Kang Figures 1 & 4-5 demonstrate sensing lines (S1-S4) comprising transverse and longitudinal segments. Each pixel structure (and its corresponding TFT) is connected to these lines. Kang explicitly describes a connection structure in the signal line transferring area (103) that uses insulation layers and openings (via holes) to connect the M1 traces to other layers.).
CLAIM 19. Kang teaches an display panel according to claim 1, wherein longitudinal widths of the plurality of M1 traces connected to each of the plurality of thin film transistors are the same (The traces (S1-S4) shown in Kang are illustrated as having uniform width. In the fabrication of array substrates, as taught by Kang, traces in the same metal layer are created with the same longitudinal width to maintain uniform impedance.).
CLAIM 20. Kang teaches an display panel according to claim 1, wherein longitudinal width of a portion of the plurality of M1 traces in the at least one of the plurality of sub-fan-out areas are the same (As addressed regarding Claim 9, Kang’s M1 traces in the fan-out and transferring areas (103, 104) are uniform. This necessitates that the longitudinal width of the portion of M1 traces in at least one sub-fan-out area is the same.).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 8 & 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kang et al. (US 2021/0089158 A1)
CLAIM 8. Kang teaches an array substrate according to claim 7, however may be silent upon wherein the plurality of via holes are arranged in parallel to avoid extended M1 traces pass through the via holes corresponding to other thin film transistors. Kang does however discloses via holes (Figs. 4-5 & ¶45) for trace connectivity. While Kang may not explicitly use the phrase "parallel to avoid extended M1 traces," it would have been obvious to a person of ordinary skill in the art to arrange via holes in a parallel or staggered configuration to prevent traces from intersecting or shorting at contact points, which is a standard practice in circuit layout.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
CLAIM 18. Kang teaches an display panel according to claim 7, however may be silent upon wherein the plurality of via holes are arranged in parallel to avoid extended M1 traces pass through the via holes corresponding to other thin film transistors. Kang does however discloses via holes (Figs. 4-5 & ¶45) for trace connectivity. While Kang may not explicitly use the phrase "parallel to avoid extended M1 traces," it would have been obvious to a person of ordinary skill in the art to arrange via holes in a parallel or staggered configuration to prevent traces from intersecting or shorting at contact points, which is a standard practice in circuit layout.
When there is a design need or market pressure to solve a problem and there are a finite number of identified, predictable solutions, a person of ordinary skill in the art has good reason to pursue the known options within his or her technical grasp. If this leads to the anticipated success, it is likely the product not of innovation but of ordinary skill and common sense. KSR Int'l Co v. Teleflex Inc.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JARRETT J STARK whose telephone number is (571)272-6005. The examiner can normally be reached 8-4 M-F.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Manno can be reached at 571-272-2339. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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JARRETT J. STARK
Primary Examiner
Art Unit 2822
8/26/2026
/JARRETT J STARK/Primary Examiner, Art Unit 2898
1 Kang - [0040] FIG. 4 is a top view of a pixel structure in accordance with an embodiment. FIG. 5 is a cross-sectional view of the pixel structure of FIG. 4 along a cross-sectional line AA′. Referring to FIG. 4, a pixel structure 410 is taken as an example. The pixel structure 410 includes a TFT 420, a pixel electrode PE and a common electrode (not shown). The TFT 420 includes a gate 420G, a source 420S and a drain 420D. A gate line 430 formed by a second metal layer M2 is connected to the gate 420G. A data line 431 formed by a third metal layer M3 is connected to the source 420S. In addition, a sensing line 432 is formed by a first metal layer M1 and is connected to the common electrode (i.e. touch electrode) through a via. The sensing line 432 is disposed at the left-hand side of the data line 431 in the embodiment, but the sensing line 432 may be disposed at the right-hand side of the data line 431 in other embodiments.
2 Kang - [0045] Referring to FIG. 4, a connection structure 450 is disposed in the signal line transferring area 103 for transferring the sensing line 432 into another metal layer. In the embodiment, the sensing line 432 includes a first portion 461 and a second portion 462. The first portion 461 is formed by the first metal layer M1, and the second portion 462 is formed by the third metal layer M3. In other words, the connection structure 450 is used to transfer the sensing line 432 from the first metal layer M1 into the third metal layer M3….
3 Kang - [0040] FIG. 4 is a top view of a pixel structure in accordance with an embodiment. FIG. 5 is a cross-sectional view of the pixel structure of FIG. 4 along a cross-sectional line AA′. Referring to FIG. 4, a pixel structure 410 is taken as an example. The pixel structure 410 includes a TFT 420, a pixel electrode PE and a common electrode (not shown). The TFT 420 includes a gate 420G, a source 420S and a drain 420D. A gate line 430 formed by a second metal layer M2 is connected to the gate 420G. A data line 431 formed by a third metal layer M3 is connected to the source 420S. In addition, a sensing line 432 is formed by a first metal layer M1 and is connected to the common electrode (i.e. touch electrode) through a via. The sensing line 432 is disposed at the left-hand side of the data line 431 in the embodiment, but the sensing line 432 may be disposed at the right-hand side of the data line 431 in other embodiments.
4 Kang - [0045] Referring to FIG. 4, a connection structure 450 is disposed in the signal line transferring area 103 for transferring the sensing line 432 into another metal layer. In the embodiment, the sensing line 432 includes a first portion 461 and a second portion 462. The first portion 461 is formed by the first metal layer M1, and the second portion 462 is formed by the third metal layer M3. In other words, the connection structure 450 is used to transfer the sensing line 432 from the first metal layer M1 into the third metal layer M3….
Prosecution Insights