DETAILED ACTION
This correspondence is in response to the communications received 01/28/2026. Claims 3, 6, 7, 13, and 16-19 have been withdrawn. Claims 1-20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of claims 1, 2, 4, 5, 8-12, 14, 15, and 20 in the reply filed on 02/18/2026 is acknowledged. The traversal is on the ground that "it should be no undue burden on Examiner to consider all claims 1-20 of the application at the same time". This is not found persuasive because as previously stated in the Requirement for Restriction/Election, several claims require mutually exclusive limitations necessitating individual searches. For example, Species A and Species B require a trench capacitor and a parallel plate capacitor respectively. These species likely would require separate searches. Species C-E each require the oxide semiconductor field effect transistor to be located in different positions relative to the capacitor, again, these species would each require a separate search as the prior art applicable to one species would not likely be applicable to another species.
The requirement is still deemed proper and is therefore made FINAL.
Claims 3, 6, 7, 13, and 16-19 have been withdrawn from further consideration pursuant to 37 CFR 1.142(b), as being drawn to nonelected species, there being no allowable generic or linking claim. Applicant timely traversed the restriction (election) requirement in the reply filed on 03/25/2026.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/30/2023, 08/28/2024, and 03/07/2025 have been considered by the examiner and made of record in the application file.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a semiconductor structure (10), comprising:
a substrate (100);
a capacitor (102) located on the substrate (see Fig. 1); and
an oxide semiconductor field effect transistor (104) located on the substrate (see Fig. 1) and electrically connected to the capacitor (see Fig. 1 where "the electrode layer 122 may be electrically connected to the electrode layer 106 by the interconnect structure 126", [0048]).
Regarding claim 8, the semiconductor structure according to claim 1, wherein the oxide semiconductor field effect transistor comprises:
a first electrode layer (116) located on the substrate (see Fig. 1);
a first dielectric layer (118) located on the first electrode layer (see Fig. 1);
a channel layer (120) located on the first dielectric layer and located above the first electrode layer (see Fig. 1); and
a second electrode layer (122) and a third electrode layer (124) located on the first dielectric layer and located on two sides of the channel layer (see Fig. 1).
Regarding claim 14, the semiconductor structure according to claim 8, wherein the capacitor is located in the substrate and comprises:
a fourth electrode layer (106) located in the substrate (see Fig. 1);
a fifth electrode layer located (108) on the fourth electrode layer (see Fig. 1);
a second dielectric layer (110) located between the fourth electrode layer and the substrate (see Fig. 1); and
a third dielectric layer (112) located between the fourth electrode layer and the fifth electrode layer (see Fig. 1).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 4, 5, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al. (US 20160095221 A1, published 03/31/2016) in view of Wang et al. (US 11,222,895 B2, published 01/11/2022) in view of Wu et al. (US 20170084614 A1, published 03/23/2017).
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Regarding claim 1, Figs. 1-6 of Ramachandran disclose a semiconductor structure (“semiconductor die 100”, [0028]), comprising:
a substrate (“substrate 104”, [0028]);
a capacitor (“trench capacitors 114”, [0029]) located on the substrate (as seen in Fig. 1, 0029 are on 104); and
an oxide semiconductor field effect transistor (“I/O transistor 108a (which may be TFTs)”, [0028], Ramachandran does not specify that 108a is an oxide semiconductor field effect transistor, however a secondary reference will be utilized to teach this limitation below) located on the substrate (as seen in Fig. 1, 108a is on 104) and electrically connected to the capacitor (Ramachandran states “Further, second side 106 may include one or more metal layers or interconnects 108d which may form interconnections between electronic elements of the second set”, [0028], but does not specifically disclose 108a is electrically connected to 114, however a secondary reference will be utilized to teach this limitation below).
Ramachandran fails to disclose “an oxide semiconductor field effect transistor … electrically connected to the capacitor”.
However, in a similar field of endeavor, Figs. 1-9 of Wang teach an oxide semiconductor field effect transistor (“TFTs can be made using a wide variety of semiconductor materials, such as silicon, germanium, silicon-germanium, as well as various oxide semiconductors (a.k.a. semiconducting oxides) including metal oxides like indium gallium zinc oxide (IGZO), indium zinc oxide (IZO), and the like”, col. 4, lines 58-63, thus 108a of Ramachandran could include an oxide semiconductor such as IGZO or IZO).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “an oxide semiconductor field effect transistor” as taught by Wang in the system of Ramachandran for the purpose of providing a composition for the active layer of the transistor.
Ramachandran in combination with Wang fails to disclose “an oxide semiconductor field effect transistor … electrically connected to the capacitor”.
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However, in a similar field of endeavor, Figs. 1 and 2 of Wu teaches an oxide semiconductor field effect transistor (“OS FET device 140”, [0016], where “The OS FET device 140 includes an oxide semiconductor (hereinafter abbreviated as OS) layer 1420S, a gate electrode 142G, a source electrode 142S, a drain electrode 142D, and a dielectric layer 144”, [0013]) … electrically connected to the capacitor (“the drain electrode 142D is electrically connected to the DT capacitor”, [0017]).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “an oxide semiconductor field effect transistor … electrically connected to the capacitor” as taught by Wu in the system of Ramachandran in combination with Wang for the purpose of describing the interconnections of the semiconductor structure.
Regarding claim 2, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang and Figs. 1 and 2 of Wu disclose the semiconductor structure according to claim 1, Figs. 1-6 of Ramachandran further disclose wherein the capacitor comprises a trench capacitor (as previously discussed, 114 is a trench capacitor).
Regarding claim 4, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang and Figs. 1 and 2 of Wu disclose the semiconductor structure according to claim 1, Figs. 1-6 of Ramachandran and Figs. 1-9 of Wang further disclose wherein the oxide semiconductor field effect transistor comprises an oxide semiconductor thin film transistor (as previously discussed, Ramachandran discloses that 108a is a thin film transistor or TFT, and Wand discloses that TFTs can be made using semiconducting oxides).
Regarding claim 5, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang and Figs. 1 and 2 of Wu disclose the semiconductor structure according to claim 1, Figs. 1-6 of Ramachandran further disclose wherein the oxide semiconductor field effect transistor is located above the capacitor (as seen in Fig. 1, 108a is above 114).
Regarding claim 20, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang and Figs. 1 and 2 of Wu disclose the semiconductor structure according to claim 1, Figs. 1-6 of Ramachandran further disclose 20. (original) The semiconductor structure according to claim 1, further comprising:
a through-substrate via (“through-silicon via (TSV) 112”, [0029]) located in the substrate and passing through the substrate (as seen in Fig. 1, 112 is located in 104 and passes through 104).
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al. (US 20160095221 A1, published 03/31/2016) in view of Wang et al. (US 11,222,895 B2, published 01/11/2022) in view of Wu et al. (US 20170084614 A1, published 03/23/2017) in view of Sharma et al. (US 11,189,733 B2, published 11/30/2021).
Regarding claim 8, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang and Figs. 1 and 2 of Wu disclose the semiconductor structure according to claim 1, Figs. 1 and 2 of Wu further disclose wherein the oxide semiconductor field effect transistor comprises:
a first electrode layer (142G is a first electrode) located on the substrate (as seen in Fig. 2, 142G is on “substrate 102”, [0013]);
a first dielectric layer (“dielectric layer 144”, [0016]);
a channel layer (“OS layer 142OS”, [0016], Wu does not specify that 142OS is a channel layer, however a secondary reference will be utilized to teach this limitation below); and
a second electrode layer (142D is a second electrode layer) and a third electrode layer (142S is a third electrode layer).
Ramachandran in combination with Wang and Wu fail to disclose “a first dielectric layer located on the first electrode layer;
a channel layer located on the first dielectric layer and located above the first electrode layer; and
a second electrode layer and a third electrode layer located on the first dielectric layer and located on two sides of the channel layer.”
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However, in a similar field of endeavor, Fig. 8 of Sharma teaches a first dielectric layer (“gate dielectric 320”, col. 16, lines 56-57, where 320 of Sharma is equivalent to 144 of Wu) located on the first electrode layer (as seen in Fig. 8, 320 is located on “gate electrode 310”, col. 16, line 56, where 310 of Sharma is equivalent to 142G of Wu);
a channel layer (“TFT layer 330”, col. 16, line 17 where “TFT layer 330 may be formed from a material of a first conductivity type, which may be an n-type or a p-type channel material”, col. 10, lines 15-17 and 330 of Sharma is equivalent to 142OS of Wu) located on the first dielectric layer (as seen in Fig. 8, 330 is located on 320) and located above the first electrode layer (as seen in Fig. 8, 330 is located above 310); and
a second electrode layer and a third electrode layer (as seen in Fig. 8, the right instance of “S/D contact structure 350”, col. 16, line 60, is a second electrode layer equivalent to 142D of Wu, and the left instance of 350 is a third electrode layer equivalent to 142S of Wu) located on the first dielectric layer (as seen in Fig. 8, 350 are located on 320) and located on two sides of the channel layer (as seen in Fig. 8, 350 are located on two sides of 330).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a first dielectric layer located on the first electrode layer;
a channel layer located on the first dielectric layer and located above the first electrode layer; and
a second electrode layer and a third electrode layer located on the first dielectric layer and located on two sides of the channel layer” as taught by Sharma in the system of Ramachandran in combination with Wang and Wu for the purpose of shrinking the device structure by spreading the electrodes from one side of the channel layer to two sides, thus enabling a smaller lateral dimension.
Regarding claim 9, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang, Figs. 1 and 2 of Wu, and Fig. 8 of Sharma disclose the semiconductor structure according to claim 8, Fig. 8 of Sharma further discloses wherein a material of the first electrode layer comprises molybdenum, titanium, tantalum, tungsten, aluminum, copper, chromium, or an alloy thereof (“Gate electrode 310, in some embodiments, may include a wide range of materials, such as various suitable metals or metal alloys, such as one or more of aluminum (Al), tungsten (W), titanium (Ti), tantalum (Ta), copper (Cu), nickel (Ni), gold (Au), platinum (Pt), ruthenium (Ru), or cobalt (Co), and/or carbides thereof and/or nitrides thereof, for example”, emphasis added, col. 7, lines 15-21).
Regarding claim 10, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang, Figs. 1 and 2 of Wu, and Fig. 8 of Sharma disclose the semiconductor structure according to claim 8, Fig. 8 of Sharma further discloses wherein a material of the first dielectric layer comprises silicon oxide, silicon nitride, or hafnium nitride (“Gate dielectric 320, in some embodiments, may include any suitable oxide (such as silicon dioxide), high-k dielectric material, low-k dielectric material, and/or any other suitable material as will be apparent in light of this disclosure. Examples of high-k dielectric materials include, for instance, hafnium oxide, hafnium silicon oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate, to provide some examples”, emphasis added, col. 8, lines 6-17).
Regarding claim 11, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang, Figs. 1 and 2 of Wu, and Fig. 8 of Sharma disclose the semiconductor structure according to claim 8, Fig. 8 of Sharma further discloses wherein a material of the channel layer comprises an oxide semiconductor, and the oxide semiconductor comprises indium gallium zinc oxide, zinc oxide, indium zinc oxide, cobalt oxide, nickel oxide, strontium copper oxide, copper aluminum oxide, copper indium oxide, or copper gallium oxide (“TFT layer 330, in some embodiments, may include at least one metal oxide, such as indium gallium zinc oxide (referred to as IGZO), gallium oxide, indium oxide, indium tin oxide (referred to as ITO), indium zinc oxide (referred to as IZO), indium molybdenum oxide (referred to as IMO), copper oxide, zinc oxide, and/or zinc tin oxide (referred to as ZTO), to name a few examples”, emphasis added, col. 9, lines 42-48).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al. (US 20160095221 A1, published 03/31/2016) in view of Wang et al. (US 11,222,895 B2, published 01/11/2022) in view of Wu et al. (US 20170084614 A1, published 03/23/2017) in view of Sharma et al. (US 11,189,733 B2, published 11/30/2021) in view of Yamazaki (US 9,443,984 B2, published 09/13/2016).
Regarding claim 12, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang, Figs. 1 and 2 of Wu, and Fig. 8 of Sharma disclose the semiconductor structure according to claim 8.
Ramachandran in combination with Wang, Wu, and Sharma fail to disclose “wherein a material of the second electrode layer and a material of the third electrode layer comprise an N-type oxide semiconductor, the N-type oxide semiconductor comprises indium gallium zinc oxide, zinc oxide, or indium zinc oxide, and the N-type oxide semiconductor has an N-type dopant.”
However, in a similar field of endeavor, Figs. 1A and 1B of Yamazaki teaches wherein a material of the second electrode layer and a material of the third electrode layer comprise an N-type oxide semiconductor, the N-type oxide semiconductor comprises indium gallium zinc oxide, zinc oxide, or indium zinc oxide, and the N-type oxide semiconductor has an N-type dopant (“Next, the source region 103a and the drain region 103b are formed by a self-aligned process. Specifically … a dopant 106 is added to the oxide semiconductor layer 103 by an ion doping method or an ion implantation method. As the dopant 106 added to the oxide semiconductor layer 103, one or more elements selected from rare gases and hydrogen (H) can be used.
Hydrogen serves as an electron donor (donor) in an oxide semiconductor and causes the oxide semiconductor to have n-type conductivity”, col. 22, lines 31-41, where 103a and 103b of Yamazaki are equivalent to 142S and 142D of Wu respectively, and 103 is formed from an “oxide semiconductor, for example, indium oxide, tin oxide, zinc oxide, a two-component metal oxide such as an In—Zn-based oxide, a Sn—Zn-based oxide, an Al—Zn-based oxide, a Zn—Mg-based oxide, a Sn—Mg-based oxide, an In—Mg-based oxide, or an In—Ga-based oxide, a three-component metal oxide such as an In—Ga—Zn-based oxide (also referred to as IGZO)…”, emphasis added, col. 10, lines 28-49).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein a material of the second electrode layer and a material of the third electrode layer comprise an N-type oxide semiconductor, the N-type oxide semiconductor comprises indium gallium zinc oxide, zinc oxide, or indium zinc oxide, and the N-type oxide semiconductor has an N-type dopant” as taught by Yamazaki in the system of Ramachandran in combination with Wang, Wu, and Sharma for the purpose of reducing the complexity of the manufacturing process by forming the source and drain regions from the same material as the channel region.
Claims 14 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Ramachandran et al. (US 20160095221 A1, published 03/31/2016) in view of Wang et al. (US 11,222,895 B2, published 01/11/2022) in view of Wu et al. (US 20170084614 A1, published 03/23/2017) in view of Sharma et al. (US 11,189,733 B2, published 11/30/2021) in view of Roozeboom et al. (US 8,085,524 B2, published 12/27/2011).
Regarding claim 14, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang, Figs. 1 and 2 of Wu, and Fig. 8 of Sharma disclose the semiconductor structure according to claim 8.
Ramachandran in combination with Wang, Wu, and Sharma fail to disclose “wherein the capacitor is located in the substrate and comprises:
a fourth electrode layer located in the substrate;
a fifth electrode layer located on the fourth electrode layer;
a second dielectric layer located between the fourth electrode layer and the substrate; and
a third dielectric layer located between the fourth electrode layer and the fifth electrode layer.”
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However, in a similar field of endeavor, Figs. 1 and 2 of Roozeboom teach wherein the capacitor is located in the substrate (as seen in Fig. 1, “trench capacitor 102”, col. 7, lines 62-63” is located in “a high-resistivity silicon substrate 104”, col. 7, lines 55-56, where 102 and 104 of Roozeboom are equivalent to 114 and 104 of Ramachandran respectively) and comprises:
a fourth electrode layer (“conductive poly-silicon layer 114”, col. 8, line 5, where “In a trench capacitor, the electrodes are formed by electrically conductive layers deposited in a recess or pore prepared in the substrate (wafer)”, col. 1, lines 20-22, thus as 114 is a conductive layer in “pore 106”, col. 8, line 3, 114 is an electrode) located in the substrate (as seen in Fig. 1, 128 is in 104);
a fifth electrode layer (“second conductive poly-silicon layer 118”, col. 8, lines 6-7 as discussed above, 118 is also an electrode) located on the fourth electrode layer (as seen in Fig. 1, 118 is located on 114);
a second dielectric layer (“first dielectric layer 112”, col. 8, line 5) located between the fourth electrode layer and the substrate (as seen in Fig. 1, 112, is located between 114 and 104); and
a third dielectric layer (“second dielectric layer 116”, col. 8, line 6) located between the fourth electrode layer and the fifth electrode layer (as seen in Fig. 1, 116 is located between 114 and 118).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “wherein the capacitor is located in the substrate and comprises:
a fourth electrode layer located in the substrate;
a fifth electrode layer located on the fourth electrode layer;
a second dielectric layer located between the fourth electrode layer and the substrate; and
a third dielectric layer located between the fourth electrode layer and the fifth electrode layer” as taught by Roozeboom in the system of Ramachandran in combination with Wang, Wu, and Sharma for the purpose of detailing the specific structure of the trench capacitor.
Regarding claim 15, Figs. 1-6 of Ramachandran in combination with Figs. 1-9 of Wang, Figs. 1 and 2 of Wu, Fig. 8 of Sharma, and Figs. 1 and 2 of Roozeboom disclose the semiconductor structure according to claim 14, Figs. 1 and 2 of Wu and Figs. 1 and 2 of Roozeboom further disclose wherein the second electrode layer is electrically connected to the fourth electrode layer (Wu states “the drain electrode 142D is electrically connected to the DT capacitor 110 as shown in FIG. 1”, [0017], further Roozeboom teaches “A better reduction of a parasitic capacitance between the floating electrode and the substrate is achieved, however, if the floating electrode is more distant from the substrate”, col. 4, lines 57-60, thus in order to minimize parasitic capacitance, one having ordinary skill in the art would electrically connect 142D of Wu to 114 of Roozeboom, as 114 of Roozeboom is the closest electrode to 104 of Roozeboom).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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