Prosecution Insights
Last updated: August 16, 2026
Application No. 18/523,936

SOI SUBSTRATE AND METHOD OF MANUFACTURING THE SAME

Final Rejection §103
Filed
Nov 30, 2023
Priority
Aug 08, 2023 — CN 202310995455.0
Examiner
SMITH, BRADLEY
Art Unit
2817
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.
OA Round
2 (Final)
80%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
77%
With Interview

Examiner Intelligence

Grants 80% — above average
80%
Career Allowance Rate
710 granted / 891 resolved
+11.7% vs TC avg
Minimal -3% lift
Without
With
+-3.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
36 currently pending
Career history
922
Total Applications
across all art units

Statute-Specific Performance

§101
2.6%
-37.4% vs TC avg
§103
43.6%
+3.6% vs TC avg
§102
22.8%
-17.2% vs TC avg
§112
24.4%
-15.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 891 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments The applicant alleges “Nishihata does not disclose that the boron ion implanted layer 15A has an electrostatic adsorption function.” The examiner notes that Nishihata did not need to recognize that the “the boron ion implanted layer 15A has an electrostatic adsorption function”. MPEP 2112 II discloses “[t]here is no requirement that a person of ordinary skill in the art would have recognized the inherent disclosure at the relevant time, but only that the subject matter is in fact inherent in the prior art reference. Schering Corp. v. Geneva Pharm. Inc., 339 F.3d 1373, 1377, 67 USPQ2d 1664, 1668 (Fed. Cir. 2003)”. Moreover, MPEP 2112.01I discloses “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).”) In this case since the combination of AAPA Wantanabe and Nishihata et al. disclose a structure formed by the same broad process by the same claimed process the combined disclosures would have the same results. Therefore, the applicant’s arguments are unpersuasive. The applicant alleges “Nishihata also does not disclose that the resistivity of the boron ion implanted layer 15A is less than that of the silicon wafer 11”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “the resistivity of the boron ion implanted layer 15A is less than that of the silicon wafer 11”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, the applicant’s arguments are unpersuasive. The applicant alleges “in Nishihata, no heat treatment is performed after the oxygen ion implantation and before the boron ion implantation, and the heat treatment occurs after the boron ion implantation” (applicant’s underline). In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “heat treatment is performed after the oxygen ion implantation and before the boron ion implantation,”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, the applicant’s arguments are unpersuasive. The applicant alleges “[t]he annealing treatment occurs after the oxygen ion implantation, and the annealing treatment also occurs after the boron ion implantation, so that two annealing treatments are performed.” In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., “[t]he annealing treatment occurs after the oxygen ion implantation, and the annealing treatment also occurs after the boron ion implantation, so that two annealing treatments are performed.”) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Therefore, the applicant’s arguments are unpersuasive. The applicant alleges “ Nishihata fails to disclose or teach ‘processing the substrate from the second surface of the substrate to sequentially form an insulating dielectric layer and an electrostatic adsorption layer; wherein a resistivity of the electrostatic adsorption layer is less than a resistivity of the substrate’". The examiner disagrees. The applicant broadly claims “processing the substrate” in claim 1. The examiner submits the annealing disclosed in Nishihata would read on the “processing the substrate”. MPEP 2112 II discloses “[t]here is no requirement that a person of ordinary skill in the art would have recognized the inherent disclosure at the relevant time, but only that the subject matter is in fact inherent in the prior art reference. Schering Corp. v. Geneva Pharm. Inc., 339 F.3d 1373, 1377, 67 USPQ2d 1664, 1668 (Fed. Cir. 2003)”. Moreover, MPEP 2112.01I discloses “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).”). Therefore, the applicant’s arguments are unpersuasive. The applicant alleges “the Office Action fails to give some articulated reasoning with some rational underpinning to support why one would combine AAPA, Wantanabe, and Nishihata.” The examiner disagrees. The examiner used the rational from MPEP 2143 I (A) Combining prior art elements according to known methods to yield predictable results. MPEP 2143 I A. discloses “The rationale to support a conclusion that the claim would have been obvious is that all the claimed elements were known in the prior art and one skilled in the art could have combined the elements as claimed by known methods with no change in their respective functions, and the combination yielded nothing more than predictable results to one of ordinary skill in the art. KSR, 550 U.S. at 416, 82 USPQ2d at 1395”. The examiner used this rational in the office action. Therefore, the applicant’s arguments are unpersuasive. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-3 and 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over the applicant’s admitted prior art (will be referred to as AAPA) in view of Wantanabe (US Patent 5,289,031) and Nishihata et al. (US 2011/0084367). The AAPA discloses providing a device wafer (specification [0004], SOI substrate); wherein the device wafer comprises a substrate (bulk substrate), a buried oxide layer (BOX)[0004], and a semiconductor layer (thin single crystal silicon); the substrate has a first surface (top surface) and a second surface (bottom surface) opposite to the first surface; the buried oxide layer and the semiconductor layer are disposed sequentially on the first surface of the substrate (figure 2 in the applicant’s specification is an example of an SOI substrate). AAPA fails to disclose processing the substrate from the second surface of the substrate. Wantanabe disclose implanting (processing) from a backside (fig. 2)[col. 6 lines 43-46]. The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (processing/implanting from the backside), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (the oxygen would be implanted/processed from the backside). AAPA and Wantanabe fail to sequentially form an insulating dielectric layer and an electrostatic adsorption layer; wherein a resistivity of the electrostatic adsorption layer is less than a resistivity of the substrate. Nishihata et al. disclose processing the substrate from a surface of the substrate to sequentially form an insulating dielectric layer (by implanting oxygen) (fig. 2)[0073] and an electrostatic adsorption layer [0074-0075](figs. 3-implanting boron)(fig. 4 annealing to activate the ions which would form the electrostatic adsorption layer because this is the same process that is disclosed in the current specification paragraphs [0055-0056]; wherein a resistivity of the electrostatic adsorption layer is less than a resistivity of the substrate (figs. 2-4 disclose the same method and structure therefore one would expect “a resistivity of the electrostatic adsorption layer is less than a resistivity of the substrate”. See MPEP 2112.01I “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).”) The combination of AAPA Wantanabe and Nishihata et al. would result in processing the second surface of the device wafer. The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (processing/implanting oxygen and boron into a substrate), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (the oxygen and boron would be implanted into the substrate and annealed). Regarding claim 2, the combination of AAPA Wantanabe and Nishihata et al. discloses implanting oxygen ions [Nishihata et al. 0073] into the substrate from the second surface (Wantanabe) and performing a first annealing process to convert a portion of the substrate into the insulating dielectric layer[Nishihata et al. 0028, 0078]; and implanting ions into the substrate [Nishihata et al. 0074, 0075] from the second surface (Wantanabe) and performing a second annealing process [0075] to convert the entirety of a portion of the substrate away from the insulating dielectric layer into the electrostatic adsorption layer. Regarding claim 3, the combination of AAPA Wantanabe and Nishihata et al. discloses the resistivity of the substrate is greater than 7000 Ohms cm, the resistivity of the electrostatic adsorption layer is less than 2000 ohms cm. (The combination of AAPA Wantanabe and Nishihata et al. disclose the same process and same materials therefore one of ordinary skill would expect the same results. See MPEP 2112.01I “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).”) Regarding claim 9, the combination of AAPA Wantanabe and Nishihata et al. discloses the insulating dielectric layer has a thickness greater than 50 nm [Nishihata et al. 0116] (discloses layer 12 is .1 mm which is 100 nanometers). Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over the applicant’s admitted prior art (will be referred to as AAPA) in view of Wantanabe (US Patent 5,289,031) and Nishihata et al. (US 2011/0084367) as applied to claim 1 above. The combination of AAPA Wantanabe and Nishihata et al. discloses forming a protective layer (13 and 14a, fig.1D) on a surface of the semiconductor layer (AAPA) away from the buried oxide layer. The combination of AAPA Wantanabe and Nishihata et al. fails to explicitly disclose after the processing the substrate from the second surface of the substrate to sequentially form an insulating dielectric layer and an electrostatic adsorption layer, the method further comprises: removing the protective layer. Wantanabe does disclose the removal (fig 1F) of the protective layer (layers 13 and 14a). However, Wantanabe does not disclose the removal of the protective layer after the processing/implanting. MPEP 2144.04 IV disclose In reBurhans, 154 F.2d 690, 69 USPQ 330 (CCPA 1946) (selection of any order of performing process steps is prima facie obvious in the absence of new or unexpected results). The examiner submits it would be obvious to remove the the protective layer (layers 13 and 14a) after the processing/implanting at the time the application was filed because the applicant has not shown any unexpected results. The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (removing the protective layer ), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (would remove the protective layer after the processing/implanting). Regarding claim 8, the combination of AAPA Wantanabe and Nishihata et al. discloses the forming a protective layer on a surface of the semiconductor layer away from the buried oxide layer, comprises: forming a silicon nitride layer (13) (Wantanabe fig 1D) on (over) the (top) surface of the semiconductor layer (APAA) away from the buried oxide layer (AAPA); and forming a silicon oxide (14a, Wantanabe fig 1D) layer on a surface of the silicon nitride layer away from the semiconductor layer. Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over the applicant’s admitted prior art (will be referred to as AAPA) in view of Wantanabe (US Patent 5,289,031) and Nishihata et al. (US 2011/0084367) as applied to claim 1 above and further in view of Shank et al. (US 2018/0096884). The combination of AAPA Wantanabe and Nishihata et al. disclose the invention supra. The combination of AAPA Wantanabe and Nishihata et al. fails to disclose a polycrystalline silicon layer is disposed between the substrate and the buried oxide layer and serves as a trap-rich layer to trap parasitic charges that are free in the buried oxide layer and the substrate. Shank et al.disclose a polycrystalline silicon layer is disposed between the substrate (handle, 102) and the buried oxide layer (104) and serves as a trap-rich layer to trap parasitic charges that are free in the buried oxide layer and the substrate (102) (abstract) (fig.4)[0040-0041]. The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (forming a polysilicon layer in between the substrate and the buried oxide ), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (polysilicon would minimize parasitic surface conductance [Shank et al. abstract]). Claim(s) 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over the applicant’s admitted prior art (will be referred to as AAPA) in view of Wantanabe (US Patent 5,289,031) and Nishihata et al. (US 2011/0084367). The AAPA discloses providing a device wafer (specification [0004], SOI substrate); wherein the device wafer comprises a substrate (bulk substrate), a buried oxide layer (BOX)[0004], and a semiconductor layer (thin single crystal silicon); the substrate has a first surface (top surface) and a second surface (bottom surface) opposite to the first surface; the buried oxide layer and the semiconductor layer are disposed sequentially on the first surface of the substrate (figure 2 in the applicant’s specification is an example of an SOI substrate). AAPA fails to disclose processing the substrate from the second surface of the substrate (ie away from the buried oxide layer side of the substrate). Wantanabe disclose implanting (processing) from a backside to form a dielectric on the backside of the substrate (fig. 2)[col. 6 lines 43-46]. The combination would result in the implanting (processing) from the backside of the substrate(ie away from the buried oxide layer side of the substrate). The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (processing/implanting from the backside to form a dielectric layer on the backside), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (the oxygen would be implanted/processed from the backside and form a dielectric layer on the backside). AAPA and Wantanabe fail to sequentially form an insulating dielectric layer and an electrostatic adsorption layer; wherein a resistivity of the electrostatic adsorption layer is less than a resistivity of the substrate. Nishihata et al. disclose processing the substrate from a surface of the substrate to sequentially form an insulating dielectric layer (by implanting oxygen) (fig. 2)[0073] and an electrostatic adsorption layer (on the insulating dielectric layer away from the substrate) [0074-0075](figs. 3-implanting boron)(fig. 4 annealing to activate the ions which would form the electrostatic adsorption layer because this is the same process that is disclosed in the current specification paragraphs [0055-0056]; wherein a resistivity of the electrostatic adsorption layer is less than a resistivity of the substrate (figs. 2-4 disclose the same method and structure therefore one would expect “a resistivity of the electrostatic adsorption layer is less than a resistivity of the substrate”. See MPEP 2112.01I “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).”) The combination of AAPA Wantanabe and Nishihata et al. would result in processing the second surface of the device wafer so as to form an electrostatic adsorption layer, laminated on a surface of the insulating dielectric layer away from the substrate, wherein a resistivity of the electrostatic adsorption layer is less than a resistivity of the substrate. (The examiner submit the combination discloses the same materials and same process steps therefore one would expect the same results. See MPEP 2112.01I “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).”) The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (processing/implanting oxygen and boron into a substrate), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (the oxygen and boron would be implanted into the substrate and annealed). Regarding claim 13, the combination of AAPA Wantanabe and Nishihata et al. discloses the insulating dielectric layer has a thickness greater than 50 nm [Nishihata et al. 0116] (discloses layer 12 is .1 mm which is 100 nanometers). Regarding claim 14, the combination of AAPA Wantanabe and Nishihata et al. discloses the resistivity of the substrate is greater than 7000 Ohms cm, the resistivity of the electrostatic adsorption layer is less than 2000 ohms cm. (The combination of AAPA Wantanabe and Nishihata et al. disclose the same process and same materials therefore one of ordinary skill would expect the same results. See MPEP 2112.01I “[w]here the claimed and prior art products are identical or substantially identical in structure or composition, or are produced by identical or substantially identical processes, a prima facie case of either anticipation or obviousness has been established. In re Best, 562 F.2d 1252, 1255, 195 USPQ 430, 433 (CCPA 1977).”) Regarding claim 15, the combination of AAPA Wantanabe and Nishihata et al. discloses the insulating dielectric is silicon oxide [Nishihata et al. 0116] Claim(s) 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over the applicant’s admitted prior art (will be referred to as AAPA) in view of Wantanabe (US Patent 5,289,031) and Nishihata et al. (US 2011/0084367) as applied to claim 12 above and further in view of Shank et al. (US 2018/0096884). The combination of AAPA Wantanabe and Nishihata et al. disclose the invention supra. The combination of AAPA Wantanabe and Nishihata et al. fails to disclose a polycrystalline silicon layer is disposed between the substrate and the buried oxide layer. Shank et al.disclose a polycrystalline silicon layer is disposed between the substrate (handle, 102) and the buried oxide layer (104) and serves as a trap-rich layer to trap parasitic charges that are free in the buried oxide layer and the substrate (102) (abstract) (fig.4)[0040-0041]. The prior art included each element claimed, although not necessarily in a single prior art reference, with the only difference between the claimed invention and the prior art being the lack of actual combination of the elements in a single prior art reference. One of ordinary skill in the art could have combined the elements as claimed by known methods (forming a polysilicon layer in between the substrate and the buried oxide ), and that in combination, each element merely performs the same function as it does separately. One of ordinary skill in the art would have recognized that the results of the combination were predictable at the time the invention was filed (polysilicon would minimize parasitic surface conductance [Shank et al. abstract]). Allowable Subject Matter Claims 4-6 and 11 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the processing the substrate from the second surface of the substrate to sequentially form an insulating dielectric layer and an electrostatic adsorption layer, comprises: forming an insulating material on the second surface of the substrate to form the insulating dielectric layer; and forming the electrostatic adsorption layer on a surface of the insulating dielectric layer away from the substrate (claims 4-6) and the oxygen ions are implanted to reach a depth of H, the insulating dielectric layer has a thickness of hl, and the electrostatic adsorption layer has a thickness of h2, and the H, the hi, and the h2 meet following equation h2=H-h1/2 (claim 11). Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to BRADLEY K SMITH whose telephone number is (571)272-1884. The examiner can normally be reached Monday-Friday, 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Marlon Fletcher can be reached at 571-272-2063. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /BRADLEY SMITH/Primary Examiner, Art Unit 2817
Read full office action

Prosecution Timeline

Nov 30, 2023
Application Filed
Apr 07, 2026
Non-Final Rejection mailed — §103
May 26, 2026
Response Filed
Jul 31, 2026
Final Rejection mailed — §103 (current)

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