DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election without traverse of Invention I, (claims 1-13 and 16-20), in the reply filed on
05/22/2026 is acknowledged. Claims 14-15 directed to the non-elected invention II are withdrawn.
Claim Objections
Claims 4 and 18 are objected to because of the following informalities: “…the passivation layer is
covered on the second gate…”. It should be read “…the passivation layer is covering the second gate…”.
Claims 7-12 are objected to because of the following informalities: “…a first gate insulating layer
covered on the first gate and the buffer layer… …a second gate insulating layer covered on the first active layer and the first gate insulating layer”. It should be read “…a first gate insulating layer
covering the first gate and the buffer layer…” …a second gate insulating layer covering the first active layer and the first gate insulating layer”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 18 and 19 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 18, it recites the limitation “…the second input electrode are disposed on a side of the passivation layer away from the second gate…” is not explained. The limitation has an antecedent issue of “the second input electrode”. Therefore, it is indefinite. For the examination purpose and according to Fig. 1, the limitation “…the second input electrode are disposed on a side of the passivation layer away from the second gate…” is interpreted as “…a second input electrode are disposed on a side of the passivation layer away from the second gate”.
Regarding claim 19, it recites the limitation “…the second input electrode is electrically connected to the second gate through the fourth via…” is not explained. The limitation has an antecedent issue of “the second input electrode”. Therefore, it is indefinite. For the examination purpose and according to Fig. 1, the limitation “…the second input electrode is electrically connected to the second gate through the fourth via…” is interpreted as “…a second input electrode is electrically connected to the second gate through the fourth via”.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-2,7-8,13, 16 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210233984 A1) in view of Kawachi (US 20230386410 A1, hereinafter Kawachi).
Re: Independent Claim 1, Wang discloses an array substrate ([0019], Fig. 1), comprising a substrate (100 [0035], Fig. 4), a first transistor (M1 drive transistor [0035], Fig. 4) and a photosensitive element (DP photodiode [0035], Fig. 4), wherein the first transistor (M1) and the photosensitive element (DP) are disposed on a same side of the substrate (100), the first transistor (M1) and the photosensitive element (DP) are electrically connected (in the array substrate all elements are electrically connected), and the first transistor (M1) comprises:
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Wang’s Figure 4-Annotated.
a first active layer (411 polysilicon layer [0103], Fig. 4) disposed away from the substrate (100);
a second gate (413 gate [0108], Fig. 4) disposed on a side of the first active layer (411);
a source and a drain (318-T top portions of connection 318 [0116], Fig. 4-Annotated), wherein the source and the drain (318-T) are disposed on a side of the second gate (413) away from the first active layer (411) and electrically connected (Fig. 4-Annotated) to the first active layer (411) respectively;
wherein the photosensitive element (DP) comprises:
a first electrode (312 first electrode [0102], Fig. 4) disposed in a same layer as the second gate (413) and electrically connected (in the array substrate all elements are electrically connected) with the source or the drain (318-T);
a photosensitive layer (314 amorphous silicon layer of the PIN-type photodiode [0107], Fig. 4) disposed on a side of the first electrode (312) away from the substrate (100); and
a second electrode (316 second electrode [0111], Fig. 4) disposed on a side of the photosensitive layer (314) away from the first electrode (312).
Wang does not expressly disclose a first gate disposed on a side of the substrate; a first active layer disposed on a side of the first gate; and a second gate away from the first gate.
However, in the same semiconductor device field of endeavor, Kawachi discloses a first gate (G2 gate [0078], Fig. 3) disposed on a side of the substrate (SUB substrate [0077], Fig. 3); a first active layer (CR channel region [0079], Fig. 3) disposed on a side of the first gate (G2); and a second gate (G1 gate [0082], Fig. 3) away from the first gate (G2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wang’s transistor to have a first gate disposed on a side of the substrate; a first active layer disposed on a side of the first gate; and a second gate away from the first gate according to Kawachi’s transistor for controlling the amount of lighting current for an OLED element ([0063], Kawachi).
Re: Claim 2, Wang modified by Kawachi discloses the array substrate of claim 1, wherein the photosensitive element (DP, Wang) further includes a first input electrode (317 connection [0116], Fig. 4, Wang), the first input electrode (317, Wang) is located at a side of the second electrode (316, Wang) away from the photosensitive layer (314, Wang) and disposed in a same layer (317 and 318-T disposed in layer 340, Fig. 12m, Wang) as the source and the drain (318-T, Wang), and the first input electrode (317, Wang) is electrically connected (Fig. 4, Wang) with the second electrode (316, Wang).
Re: Claim 7, Wang modified by Kawachi discloses the array substrate of claim 1, wherein the array substrate further comprises: a buffer layer (311 [0101], Fig. 12a-g, Wang) disposed between the substrate (100, Wang, Fig. 4) and the first gate (Kawachi’s G2-Wang modified by Kawachi’s Fig. 3);
Wang modified by Kawachi does not expressly disclose a first gate insulating layer covering the first gate and the buffer layer; and a second gate insulating layer covering the first active layer and the first gate insulating layer, wherein the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer.
However, in the same semiconductor device field of endeavor, Kawachi discloses a first gate insulating layer (GI2 gate insulating layer [0078], Fig. 3) covering the first gate (G2) and the buffer layer (UL undercoat layer [0077], Fig. 3); and a second gate insulating layer (GI1 gate insulating layer [0083], Fig. 3) covering the first active layer (CR channel region [0079], Fig. 3) and the first gate insulating layer (GI2), wherein the second gate (G1) is disposed on a side of the second gate insulating layer (GI1) away from the first gate insulating layer (GI2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wang’s transistor to have a first gate insulating layer covering the first gate and the buffer layer; and a second gate insulating layer covering the first active layer and the first gate insulating layer, wherein the second gate is disposed on a side of the second gate insulating layer away from the first gate insulating layer according to Kawachi’s transistor to obtain wherein the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer for controlling the amount of lighting current for an OLED element ([0063], Kawachi).
Re: Claim 8, Wang modified by Kawachi discloses the array substrate of claim 2, wherein the array substrate further comprises: a buffer layer (311 [0101], Fig. 12a-g, Wang) disposed between the substrate (100, Wang, Fig. 4) and the first gate (Kawachi’s G2-Wang modified by Kawachi’s Fig. 3);
Wang modified by Kawachi does not expressly disclose a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer.
However, in the same semiconductor device field of endeavor, Kawachi discloses a first gate insulating layer (GI2 gate insulating layer [0078], Fig. 3) covering the first gate (G2) and the buffer layer (UL undercoat layer [0077], Fig. 3); a second gate insulating layer (GI1 gate insulating layer [0083], Fig. 3) covering the first active layer (CR channel region [0079], Fig. 3) and the first gate insulating layer (GI2), the second gate (G1) is disposed on a side of the second gate insulating layer (GI1) away from the first gate insulating layer (GI2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wang’s transistor to have a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate is disposed on a side of the second gate insulating layer away from the first gate insulating layer according to Kawachi’s transistor to obtain the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer for controlling the amount of lighting current for an OLED element ([0063], Kawachi).
Re: Independent Claim 13, Wang discloses a display panel, comprising an array substrate ([0019], Fig. 1), wherein the array substrate comprises a substrate (100 [0035], Fig. 4), a first transistor (M1 drive transistor [0035], Fig. 4) and a photosensitive element (DP photodiode [0035], Fig. 4), wherein the first transistor (M1) and the photosensitive element (DP) are disposed on a same side of the substrate (100), the first transistor (M1) and the photosensitive element (DP) are electrically connected (in the array substrate all elements are electrically connected), and the first transistor (M1) comprises:
a first active layer (411 polysilicon layer [0103], Fig. 4) disposed away from the substrate (100);
a second gate (413 gate [0108], Fig. 4) disposed on a side of the first active layer (411);
a source and a drain (318-T top portions of connection 318 [0116], Fig. 4-Annotated), wherein the source and the drain (318-T) are disposed on a side of the second gate (413) away from the first active layer (411) and electrically connected (Fig. 4-Annotated) to the first active layer (411) respectively;
wherein the photosensitive element (DP) comprises:
a first electrode (312 first electrode [0102], Fig. 4) disposed in a same layer as the second gate (413) and electrically connected (in the array substrate all elements are electrically connected) with the source or the drain (318-T);
a photosensitive layer (314 amorphous silicon layer of the PIN-type photodiode [0107], Fig. 4) disposed on a side of the first electrode (312) away from the substrate (100); and
a second electrode (316 second electrode [0111], Fig. 4) disposed on a side of the photosensitive layer (314) away from the first electrode (312).
Wang does not expressly disclose a first gate disposed on a side of the substrate; a first active layer disposed on a side of the first gate; and a second gate away from the first gate.
However, in the same semiconductor device field of endeavor, Kawachi discloses a first gate (G2 gate [0078], Fig. 3) disposed on a side of the substrate (SUB substrate [0077], Fig. 3); a first active layer (CR channel region [0079], Fig. 3) disposed on a side of the first gate (G2); and a second gate (G1 gate [0082], Fig. 3) away from the first gate (G2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wang’s transistor to have a first gate disposed on a side of the substrate; a first active layer disposed on a side of the first gate; and a second gate away from the first gate according to Kawachi’s transistor for controlling the amount of lighting current for an OLED element ([0063], Kawachi).
Re: Claim 16, Wang modified by Kawachi discloses the display panel of claim 13, wherein the photosensitive element (DP, Wang) further includes a first input electrode (317 connection [0116], Fig. 4, Wang), the first input electrode (317, Wang) is located at a side of the second electrode (316, Wang) away from the photosensitive layer (314, Wang) and disposed in a same layer (317 and 318-T disposed in layer 340, Fig. 12m, Wang) as the source and the drain (318-T, Wang), and the first input electrode (317, Wang) is electrically connected (Fig. 4, Wang) with the second electrode (316, Wang).
Re: Claim 20, Wang modified by Kawachi, discloses the display panel of claim 13, wherein the first active layer (411, Wang) comprises a channel (channel, [0017,0087], Fig. 4, Wang), a source area and a drain area (source region and a drain region on sides of 411, [0017], Fig. 4, Wang); the source area and the drain area (Fig. 4, Wang) are located on a respective side of the channel (Fig. 4, Wang); an orthographic projection of the second gate (411, Wang) on the substrate (100, Wang) covers an orthographic projection of the channel (Fig. 4, Wang) on the substrate (100, Wang); the source (Fig. 4, Wang) is electrically connected to the source area through a corresponding first via (V1, Fig. 4-Annotated, Wang), and the drain is electrically connected to the drain area through another corresponding first via (V1, Fig. 4-Annotated, Wang).
Claim(s) 3-4, 9-10, 17 and 18 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210233984 A1) in view of Kawachi (US 20230386410 A1, hereinafter Kawachi) and further in view of Tseng et al. (US 20070257250 A1, hereinafter Tseng).
Re: Claim 3, Wang modified by Kawachi discloses the array substrate of claim 2,
Wang modified by Kawachi does not expressly disclose wherein the first transistor further comprises a second input electrode disposed in the same layer as the source and the drain; and the second input electrode is electrically connected to the second gate.
However, in the same semiconductor device field of endeavor, Tseng discloses wherein the first transistor (330 transistor gate 330 [0026], Fig. 3O) further comprises a second input electrode (356-T a top portion of conductive contacts 356 [0034], Fig. 3O-Annotated) disposed in the same layer (Fig. 3O-Annotated) as the source and the drain (356-T-L-R a top portion of conductive contacts 356 on left and right side [0034], Fig. 3O-Annotated); and the second input electrode (356-T) is electrically connected (356-via a bottom portion of 356 as a via, connecting 356-T to 330, Fig. 3O-Annotated) to the second gate (330 gate [0026], Fig. 3O).
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Tseng’s Figure 3O-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tseng’s feature wherein the first transistor further comprises a second input electrode disposed in the same layer as the source and the drain; and the second input electrode is electrically connected to the second gate to the combination of Wang and Kawachi to improve the electrical connection of the display for forming conductive contacts ([0034], Tseng).
Re: Claim 4, Wang modified by Kawachi and Tseng discloses the array substrate of claim 3, wherein the array substrate further includes a passivation layer (320 interlayer dielectric layer [0113], Fig. 12j, Wang), and the passivation layer (320, Wang) is covering the second gate (413, Wang), the first electrode (312, Wang) and the second electrode (316, Wang); wherein the source (318-T, Wang), the drain (318-T, Wang), the first input electrode (317, Wang) and the second input electrode (Tseng’s 356-T applied to Wang) are disposed on a side of the passivation layer (320, Wang) away from the second gate (413, Wang).
Re: Claim 9, Wang modified by Kawachi and Tseng discloses the array substrate of claim 3, wherein the array substrate further comprises: a buffer layer (311 [0101], Fig. 12a-g, Wang) disposed between the substrate (100, Wang, Fig. 4) and the first gate (Kawachi’s G2-Wang modified by Kawachi’s Fig. 3);
Wang modified by Kawachi does not expressly disclose a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer.
However, in the same semiconductor device field of endeavor, Kawachi discloses a first gate insulating layer (GI2 gate insulating layer [0078], Fig. 3) covering the first gate (G2) and the buffer layer (UL undercoat layer [0077], Fig. 3); a second gate insulating layer (GI1 gate insulating layer [0083], Fig. 3) covering the first active layer (CR channel region [0079], Fig. 3) and the first gate insulating layer (GI2), the second gate (G1) is disposed on a side of the second gate insulating layer (GI1) away from the first gate insulating layer (GI2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wang’s transistor to have a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate is disposed on a side of the second gate insulating layer away from the first gate insulating layer according to Kawachi’s transistor to obtain the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer for controlling the amount of lighting current for an OLED element ([0063], Kawachi).
Re: Claim 10, Wang modified by Kawachi and Tseng discloses the array substrate of claim 4, wherein the array substrate further comprises: a buffer layer (311 [0101], Fig. 12a-g, Wang) disposed between the substrate (100, Wang, Fig. 4) and the first gate (Kawachi’s G2-Wang modified by Kawachi’s Fig. 3);
Wang modified by Kawachi and Tseng does not expressly disclose a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer.
However, in the same semiconductor device field of endeavor, Kawachi discloses a first gate insulating layer (GI2 gate insulating layer [0078], Fig. 3) covering the first gate (G2) and the buffer layer (UL undercoat layer [0077], Fig. 3); a second gate insulating layer (GI1 gate insulating layer [0083], Fig. 3) covering the first active layer (CR channel region [0079], Fig. 3) and the first gate insulating layer (GI2), the second gate (G1) is disposed on a side of the second gate insulating layer (GI1) away from the first gate insulating layer (GI2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wang’s transistor to have a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate is disposed on a side of the second gate insulating layer away from the first gate insulating layer according to Kawachi’s transistor to obtain the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer for controlling the amount of lighting current for an OLED element ([0063], Kawachi).
Re: Claim 17, Wang modified by Kawachi discloses the display panel of claim 13,
Wang modified by Kawachi does not expressly disclose wherein the first transistor further comprises a second input electrode disposed in the same layer as the source and the drain; and the second input electrode is electrically connected to the second gate.
However, in the same semiconductor device field of endeavor, Tseng discloses wherein the first transistor (330 transistor gate 330 [0026], Fig. 3O) further comprises a second input electrode (356-T a top portion of conductive contacts 356 [0034], Fig. 3O-Annotated) disposed in the same layer (Fig. 3O-Annotated) as the source and the drain (356-T-L-R a top portion of conductive contacts 356 on left and right side [0034], Fig. 3O-Annotated); and the second input electrode (356-T) is electrically connected (356-via a bottom portion of 356 as a via, connecting 356-T to 330, Fig. 3O-Annotated) to the second gate (330 gate [0026], Fig. 3O).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tseng’s feature wherein the first transistor further comprises a second input electrode disposed in the same layer as the source and the drain; and the second input electrode is electrically connected to the second gate to the combination of Wang and Kawachi to improve the electrical connection of the display for forming conductive contacts ([0034], Tseng).
Re: Claim 18, Wang modified by Kawachi discloses the display panel of claim 13, wherein the array substrate further includes a passivation layer (320 interlayer dielectric layer [0113], Fig. 12j, Wang), and the passivation layer (320, Wang) is covering the second gate (413, Wang), the first electrode (312, Wang) and the second electrode (316, Wang); wherein the source (318-T, Wang), the drain (318-T, Wang), the first input electrode (317, Wang) are disposed on a side of the passivation layer (320, Wang) away from the second gate (413, Wang).
Wang modified by Kawachi does not expressly disclose a second input electrode disposed on a side of the passivation layer away from the second gate.
However, in the same semiconductor device field of endeavor, Tseng discloses a second input electrode (356-T a top portion of conductive contacts 356 [0034], Fig. 3O-Annotated) disposed on a side of the passivation layer (348 dielectric layer [0029], Fig. 3O) away from the second gate (330 gate [0026], Fig. 3O).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tseng’s feature of a second input electrode disposed on a side of the passivation layer away from the second gate to the combination of Wang and Kawachi to improve the electrical connection of the display for forming conductive contacts ([0034], Tseng).
Claim(s) 5-6, 11 and 12 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210233984 A1) in view of Kawachi (US 20230386410 A1, hereinafter Kawachi), in view of Tseng et al. (US 20070257250 A1, hereinafter Tseng) and further in view of Jeon (US 20220131018 A1, hereinafter Jeon).
Re: Claim 5, Wang modified by Kawachi and Tseng discloses the array substrate of claim 4, wherein the passivation layer (320, Wang) includes a first via (V1, Fig. 4-Annotated, Wang), a third via (V3, Fig. 4-Annotated, Wang) and a fourth via (Tseng’s 356-via applied to Wang and showed as V4 in Fig. 4-Annotated, Wang); wherein the source and the drain (318-T, Wang) are electrically connected to the first active layer (411, Wang) through a corresponding first via (V1, Fig. 4-Annotated, Wang); the first input electrode (317, Wang) is electrically connected to the second electrode (316, Wang) through the third via (V3, Fig. 4-Annotated, Wang); and the second input electrode (Tseng’s 356-T applied to Wang) is electrically connected to the second gate (413, Wang) through the fourth via (Tseng’s 356-via applied to Wang and showed as V4 in Fig. 4-Annotated, Wang).
Wang modified by Kawachi and Tseng does not expressly disclose wherein the passivation layer includes a second via, wherein the source or the drain is electrically connected to the first electrode through the second via.
However, in the same semiconductor device field of endeavor, Jeon discloses wherein the passivation layer (INS2 insulating layer [0127], Fig. 5) includes a second via (CE2-via-PCE a vertical portion of CE2 on PCE such a via [0128], Fig. 5-Annotated), wherein the source or the drain (CE2-S-D a horizontal portion of CE2 on D2 and INS2 such a source and drain contact [0128], Fig. 5-Annotated) is electrically connected to the first electrode (PCE sensing electrode [0119], Fig. 5) through the second via (CE2-via-PCE).
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Jeon’s Figure 5-Annotated.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeon’s feature wherein the passivation layer includes a second via, wherein the source or the drain is electrically connected to the first electrode through the second via to the combination of Wang, Kawachi and Tseng to improve the electrical connection of the display for connecting directly the source/drain contacts with the first electrode ([0128], Jeon).
Re: Claim 6, Wang modified by Kawachi, Tseng and Jeon discloses the array substrate of claim 5, wherein the first active layer (411, Wang) comprises a channel (channel, [0017,0087], Fig. 4, Wang), a source area and a drain area (source region and a drain region on sides of 411, [0017], Fig. 4, Wang); the source area and the drain area (Fig. 4, Wang) are located on a respective side of the channel (Fig. 4, Wang); an orthographic projection of the second gate (411, Wang) on the substrate (100, Wang) covers an orthographic projection of the channel (Fig. 4, Wang) on the substrate (100, Wang); the source (Fig. 4, Wang) is electrically connected to the source area through a corresponding first via (V1, Fig. 4-Annotated, Wang), and the drain is electrically connected to the drain area through another corresponding first via (V1, Fig. 4-Annotated, Wang).
Re: Claim 11, Wang modified by Kawachi, Tseng and Jeon disclose the array substrate of claim 5, wherein the array substrate further comprises: a buffer layer (311 [0101], Fig. 12a-g, Wang) disposed between the substrate (100, Wang, Fig. 4) and the first gate (Kawachi’s G2-Wang modified by Kawachi’s Fig. 3);
Wang modified by Kawachi, Tseng and Jeon does not expressly disclose a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer.
However, in the same semiconductor device field of endeavor, Kawachi discloses a first gate insulating layer (GI2 gate insulating layer [0078], Fig. 3) covering the first gate (G2) and the buffer layer (UL undercoat layer [0077], Fig. 3); a second gate insulating layer (GI1 gate insulating layer [0083], Fig. 3) covering the first active layer (CR channel region [0079], Fig. 3) and the first gate insulating layer (GI2), the second gate (G1) is disposed on a side of the second gate insulating layer (GI1) away from the first gate insulating layer (GI2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wang’s transistor to have a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate is disposed on a side of the second gate insulating layer away from the first gate insulating layer according to Kawachi’s transistor to obtain the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer for controlling the amount of lighting current for an OLED element ([0063], Kawachi).
Re: Claim 12, Wang modified by Kawachi, Tseng and Jeon disclose the array substrate of claim 6, wherein the array substrate further comprises: a buffer layer (311 [0101], Fig. 12a-g, Wang) disposed between the substrate (100, Wang, Fig. 4) and the first gate (Kawachi’s G2-Wang modified by Kawachi’s Fig. 3);
Wang modified by Kawachi, Tseng and Jeon does not expressly disclose a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer.
However, in the same semiconductor device field of endeavor, Kawachi discloses a first gate insulating layer (GI2 gate insulating layer [0078], Fig. 3) covering the first gate (G2) and the buffer layer (UL undercoat layer [0077], Fig. 3); a second gate insulating layer (GI1 gate insulating layer [0083], Fig. 3) covering the first active layer (CR channel region [0079], Fig. 3) and the first gate insulating layer (GI2), the second gate (G1) is disposed on a side of the second gate insulating layer (GI1) away from the first gate insulating layer (GI2).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to made the Wang’s transistor to have a first gate insulating layer covering the first gate and the buffer layer; a second gate insulating layer covering the first active layer and the first gate insulating layer, the second gate is disposed on a side of the second gate insulating layer away from the first gate insulating layer according to Kawachi’s transistor to obtain the second gate and the first electrode are disposed on a side of the second gate insulating layer away from the first gate insulating layer for controlling the amount of lighting current for an OLED element ([0063], Kawachi).
Claim(s) 19 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Wang et al. (US 20210233984 A1), in view of Kawachi (US 20230386410 A1, hereinafter Kawachi), in view of Jeon (US 20220131018 A1, hereinafter Jeon) and further in view of Tseng et al. (US 20070257250 A1, hereinafter Tseng).
Re: Claim 19, Wang modified by Kawachi discloses the display panel of claim 13, wherein the passivation layer (320, Wang) includes a first via (V1, Fig. 4-Annotated, Wang) and a third via (V3, Fig. 4-Annotated, Wang); wherein the source and the drain (318-T, Wang) are electrically connected to the first active layer (411, Wang) through a corresponding first via (V1, Fig. 4-Annotated, Wang); the first input electrode (317, Wang) is electrically connected to the second electrode (316, Wang) through the third via (V3, Fig. 4-Annotated, Wang).
Wang modified by Kawachi does not expressly disclose wherein the passivation layer includes a second via and a fourth via, wherein the source or the drain is electrically connected to the first electrode through the second via and a second input electrode is electrically connected to the second gate through the fourth via.
However, in the same semiconductor device field of endeavor, Jeon discloses wherein the passivation layer (INS2 insulating layer [0127], Fig. 5) includes a second via (CE2-via-PCE a vertical portion of CE2 on PCE such a via [0128], Fig. 5-Annotated), wherein the source or the drain (CE2-S-D a horizontal portion of CE2 on D2 and INS2 such a source and drain contact [0128], Fig. 5-Annotated) is electrically connected to the first electrode (PCE sensing electrode [0119], Fig. 5) through the second via (CE2-via-PCE).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Jeon’s feature wherein the passivation layer includes a second via, wherein the source or the drain is electrically connected to the first electrode through the second via to the combination of Wang and Kawachi to improve the electrical connection of the display for connecting directly the source/drain contacts with the first electrode ([0128], Jeon).
Still, Wang modified by Kawachi and Jeon does not expressly disclose a fourth via, wherein a second input electrode is electrically connected to the second gate through the fourth via.
However, in the same semiconductor device field of endeavor, Tseng discloses a fourth via (356-via a bottom portion of 356 as a via, connecting 356-T to 330, Fig. 3O-Annotated), wherein a second input electrode (356-T a top portion of conductive contacts 356 [0034], Fig. 3O-Annotated) is electrically connected to the second gate (330 gate [0026], Fig. 3O) through the fourth via (356-via).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include the Tseng’s feature of a fourth via, wherein a second input electrode is electrically connected to the second gate through the fourth via to the combination of Wang, Kawachi and Jeon to improve the electrical connection of the display for forming conductive contacts ([0034], Tseng).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Tong et al. (US 20240185792 A1) teaches “DISPLAY PANEL, DISPLAY DEVICE, AND METHOD FOR MANUFACTURING DISPLAY PANEL”. This document is related to a display panel including: a base substrate; a pixel circuit on the base substrate, the pixel circuit includes a transistor including an active layer, a gate electrode, a first electrode and a second electrode; and a fingerprint recognition circuit including a photosensitive circuit, a storage circuit and an output circuit, the storage circuit includes a first capacitor including a first capacitance electrode and a second capacitance electrode; the first capacitance electrode is arranged in the same layer as at least one of the gate electrode, the active layer, the first capacitor or the second electrode, and/or, the second capacitance electrode is arranged in the same layer as at least one of the gate electrode, the active layer, the first electrode or the second electrode; the first capacitance electrode is located in a layer different from a layer where the second capacitance electrode is located..
Song et al. (US 20210335238 A1) teaches “PIXEL UNIT, COMPENSATION METHOD OF PIXEL UNIT, DISPLAY DEVICE AND MANUFACTURING METHOD OF DISPLAY DEVICE”. This document is related to a pixel unit, a compensation method of the pixel unit, a display device and a manufacturing method of the display device are disclosed. The pixel unit includes a light-emitting circuit configured to emit light under control of an external control circuit, a photosensitive element configured to sense a light intensity of light emitted by the light-emitting circuit and to output a sensed light intensity signal by a sensing output terminal, and a switch circuit configured to control an ON/OFF state between the sensing output terminal and the external control circuit.
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/SANDRA MILENA RODRIGUEZ VILLANUEVA/Examiner, Art Unit 2898
/JESSICA S MANNO/SPE, Art Unit 2898
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