Prosecution Insights
Last updated: April 19, 2026
Application No. 18/523,952

DISPLAY PANEL

Non-Final OA §103
Filed
Nov 30, 2023
Examiner
CORNELY, JOHN PATRICK
Art Unit
2812
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Guangzhou China Star Optoelectronics Semiconductor Display Technology Co. Ltd.
OA Round
1 (Non-Final)
73%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
92%
With Interview

Examiner Intelligence

Grants 73% — above average
73%
Career Allow Rate
49 granted / 67 resolved
+5.1% vs TC avg
Strong +19% interview lift
Without
With
+19.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
22 currently pending
Career history
89
Total Applications
across all art units

Statute-Specific Performance

§103
49.6%
+9.6% vs TC avg
§102
25.3%
-14.7% vs TC avg
§112
22.0%
-18.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 67 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. An English language translation of the non-English language foreign application has not been received. Status of Claims Claims 1-20 are pending. Claims 1-20 are original. Claims 1-6, 10-14 and 18-20 is/are rejected herein. Claims 7-9 and 15-17 are objected to herein. Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: DISPLAY PANEL WITH FIRST AND SECOND PIXEL REGIONS HAVING DIFFERENT SIZE LIGHT EMITTING DEVICES. Claim Objections Claims 3 and 11 are objected to because of the following informalities: the claims recite the limitation “the light emitting devices arranged in a quantity M of row sets along a second direction” in lines 2-3 and lines 22-23, respectively. The foregoing is grammatically incorrect. It appears the foregoing should be “the light emitting devices are arranged in a quantity M of row sets along a second direction” and will be read as such for examination purposes. Appropriate correction is required. Claims 6 and 14 are objected to because of the following informalities: the claims include the symbol “上” in line 3. The foregoing appears to be a typographical error and for examination purposes it shall be deemed that the symbol is not there. Appropriate correction is required. Claim 20 is objected to under 37 CFR 1.75 as being a substantial duplicate of claim 13. When two claims in an application are duplicates or else are so close in content that they both cover the same thing, despite a slight difference in wording, it is proper after allowing one claim to object to the other as being a substantial duplicate of the allowed claim. See MPEP § 608.01(m). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-4 and 11-12 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 20190043940 A1) in view of Jeon (US 20210202686 A1). Regarding claim 1, Lee discloses (see generally, e.g., FIG. 1A and annotated FIG. 5 herein): A display panel (101), comprising a pixel region (151, 152) defined in the display panel (101), wherein the pixel region (151, 152) comprises a first region (151) and a second region (152), and the display panel (101) further comprises: a plurality of light emitting devices (107, 109, 111) disposed in the first region (151) and the second region (152) (note, in FIG. 5 the light emitting devices are illustrated but are not labeled with the corresponding reference characters, however, they are label with corresponding reference characters, e.g., in FIG. 1A); a signal connection line (see paragraph [0024] – note, the “various wiring lines” of the “wiring layer” read on the claimed signal connection line and are hereinafter referenced by “SCL”); and an area of an orthographic projection of the light emitting devices (107, 109, 111) in the second region (152) on a plane in which the display panel (101) is located is greater than an area of an orthographic projection of the light emitting devices (107, 109, 111) in the first region (151) on the plane in which the display panel (101) is located (see FIG. 5). Lee does not explicitly disclose: a signal input terminal disposed in the first region, wherein the signal input terminal is sequentially connected to the light emitting devices (107, 109, 111) in the first region (151) and the light emitting devices (107, 109, 111) in the second region (152) through the signal connection line (SCL). However, in analogous art, Jeon discloses (see generally, e.g., FIGS. 1A and 6): a signal input terminal (CPP1) disposed in the first region (PAo), wherein the signal input terminal (CPP1) is sequentially connected to the light emitting devices (Po, Pi) in the first region (PAo) and the light emitting devices (Po, Pi) in the second region (PAi) through the signal connection line (CPL). See also, e.g., paragraphs [0205]-[0206]. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a signal terminal as taught by Jeon in the first region (151) of the display panel (101) of Lee, wherein the signal terminal is sequentially connected to the light emitting devices (107, 109, 111) in the first region (151) of Lee and the light emitting devices (107, 109, 111) in the second region (152) of Lee through the signal connection line (SCL) of Lee according to known methods to yield predictable results, for example, to provide an input through which electrical signals can be supplied to drive and/or operate the light emitting devices. The conclusion of obviousness is further supported by an “obvious to try” rational. See, e.g., MPEP § 2143(I)(E). In particular, it is found that: (1) at the relevant time, there had been a recognized problem or need in the art, namely, a need to supply a signal to drive and/or operate the light emitting devices in first and second regions of a display panel; (2) there had been a finite number of identified, predictable potential solutions to the recognized need or problem, e.g., (i) disposing a signal input terminal in the first region so as to be sequentially connected to the light emitting devices in the first region and the light emitting devices in the second region, or (ii) disposing a signal input terminal in the second region so as to be sequentially connected to the light emitting devices in the second region and the light emitting devices in the first region; and (3) one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success. [AltContent: textbox (RS2)][AltContent: ][AltContent: textbox (RS1)][AltContent: ][AltContent: textbox (CS2)][AltContent: textbox (CS1)] PNG media_image1.png 1129 626 media_image1.png Greyscale ANNOTATED FIG. 5 OF LEE Regarding claim 2, Lee in view of Jeon as applied to claim 1 discloses the display panel according to claim 1. Lee further discloses wherein: the first region (151) and the second region (152) are disposed along a first direction (x), the light emitting devices (107, 109, 111) in the second region (152) are arranged in a quantity N of column sets (CS1, CS2) along the first direction (x), wherein N is an integer (i.e., 2) greater than 1; and along a direction (x) from a location near the signal input terminal to a location away from the signal input terminal (note, as modified in accordance with the teachings of Jeon, the signal terminal is disposed in the first region (151) of Lee), an area of an orthographic projection of the light emitting devices (107, 109, 111) of a (i-1)th one (i.e., 1st one – CS1) of the column sets (CS1, CS2) on the plane in which the display panel (101) is located is less than an area of an orthographic projection of the light emitting devices (107, 109, 111) of an ith one (i.e., 2nd one – CS2) of the column sets (CS1, CS2) on the plane in which the display panel (101) is located, wherein i (i.e., i=2) is equal to N. Regarding claim 3, Lee in view of Jeon as applied to claim 1 discloses the display panel according to claim 1. Lee further discloses wherein: the light emitting devices (107, 109, 111) arranged in a quantity M of row sets (RS1, RS2) along a second direction (y), wherein M is an integer (i.e., 2) greater than 1, the second direction (y) intersects the first direction (x); and along a direction (y) from a location near the signal input terminal to a location away from the signal input terminal, an area of an orthographic projection of the light emitting devices of a (j-1)th one (i.e., 1st one – RS1) of the row sets (RS1, RS2) on the plane in which the display panel (101) is located is less than an area of an orthographic projection of the light emitting devices of a jth one (i.e., 2nd one – RS2) of the row sets (RS1, RS2) on the plane in which the display panel (101) is located, wherein j (i.e., j=2) is equal to M. Note, while Lee does not explicitly disclose a specific location of the signal input terminal within the first region, Jeon does explicitly disclose a pad part (110), i.e., including the signal input terminal (CPP1), disposed in the first region (PAo) near and/or along an upper edge thereof. See, e.g., FIG. 1a and paragraphs [0110]-[0111]. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included the signal input terminal as taught by Jeon near the upper edge in the first region (151) of the display panel (101) of Lee, according to known methods to yield predictable results, for example, so that the signal input terminal does not interfere with the light emitting devices while still being included within the display area, and thus, a non-display area (or a bezel area) may not be formed. See, e.g., paragraph [0111] of Jeon. When the signal input terminal is so disposed near the upper edge in the first region (151) of Lee as taught be Jeon, the row sets (RS1, RS2) are arranged as claimed, i.e., along a direction (y) from a location near the signal input terminal (i.e., near the upper edge) to a location away (i.e., downward) from the signal input terminal. Regarding claim 4, Lee in view of Jeon as applied to claim 3 discloses the display panel according to claim 3. Lee in view of Jeon further discloses wherein each of the row sets (RS1, RS2 – see, e.g., annotated FIG. 5 of Lee herein) is at least connected to one of the signal connection lines (CPL, SPL, LCP – see, e.g., FIG. 6 of Jeon), and currents of a plurality of the signal connection lines (CPL, SPL, LCP – see, e.g., FIG. 6 of Jeon) are equal. Regarding claim 11, Lee discloses (see generally, e.g., FIG. 1A and annotated FIG. 5 herein): A display panel (101), comprising a pixel region (151, 152) defined in the display panel (101), wherein the pixel region (151, 152) comprises a first region (151) and a second region (152), and the display panel (101) further comprises: a plurality of light emitting devices (107, 109, 111) disposed in the first region (151) and the second region (152) (note, in FIG. 5 the light emitting devices are illustrated but are not labeled with the corresponding reference characters, however, they are label with corresponding reference characters, e.g., in FIG. 1A); and a signal connection line (see paragraph [0024] – note, the “various wiring lines” of the “wiring layer” read on the claimed signal connection line and are hereinafter referenced by “SCL”); and an area of an orthographic projection of the light emitting devices (107, 109, 111) in the second region (152) on a plane in which the display panel (101) is located is greater than an area of an orthographic projection of the light emitting devices (107, 109, 111) in the first region (151) on the plane in which the display panel (101) is located (see FIG. 5). Lee does not explicitly disclose: a signal input terminal disposed in the first region, wherein the signal input terminal is sequentially connected to the light emitting devices (107, 109, 111) in the first region (151) and the light emitting devices (107, 109, 111) in the second region (152) through the signal connection line (SCL). However, in analogous art, Jeon discloses (see generally, e.g., FIGS. 1A and 6): a signal input terminal (CPP1) disposed in the first region (PAo), wherein the signal input terminal (CPP1) is sequentially connected to the light emitting devices (Po, Pi) in the first region (PAo) and the light emitting devices (Po, Pi) in the second region (PAi) through the signal connection line (CPL). See also, e.g., paragraphs [0205]-[0206]. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a signal terminal as taught by Jeon in the first region (151) of the display panel (101) of Lee, wherein the signal terminal is sequentially connected to the light emitting devices (107, 109, 111) in the first region (151) of Lee and the light emitting devices (107, 109, 111) in the second region (152) of Lee through the signal connection line (SCL) of Lee according to known methods to yield predictable results, for example, to provide an input through which electrical signals can be supplied to drive and/or operate the light emitting devices. The conclusion of obviousness is further supported by an “obvious to try” rational. See, e.g., MPEP § 2143(I)(E). In particular, it is found that: (1) at the relevant time, there had been a recognized problem or need in the art, namely, a need to supply a signal to drive and/or operate the light emitting devices in first and second regions of a display panel; (2) there had been a finite number of identified, predictable potential solutions to the recognized need or problem, e.g., (i) disposing a signal input terminal in the first region so as to be sequentially connected to the light emitting devices in the first region and the light emitting devices in the second region, or (ii) disposing a signal input terminal in the second region so as to be sequentially connected to the light emitting devices in the second region and the light emitting devices in the first region; and (3) one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success. Lee further discloses: wherein the first region (151) and the second region (152) are disposed along a first direction (x), the light emitting devices (107, 109, 111) in the second region (152) are arranged in a quantity N of column sets (CS1, CS2) along the first direction (x), wherein N is an integer (i.e., 2) greater than 1; wherein along a direction (x) from a location near the signal input terminal to a location away from the signal input terminal (note, as modified in accordance with the teachings of Jeon, the signal terminal is disposed in the first region (151) of Lee) , an area of an orthographic projection of the light emitting devices (107, 109, 111) of a (i-1)th one (i.e., 1st one – CS1) of the column sets (CS1, CS2) on the plane in which the display panel (101) is located is less than an area of an orthographic projection of the light emitting devices (107, 109, 111) of an ith one (i.e., 2nd one – CS2) of the column sets (CS1, CS2) on the plane in which the display panel (101) is located, wherein i (i.e., i=2) is equal to N; wherein the light emitting devices (107, 109, 111) arranged in a quantity M of row sets (RS1, RS2) along a second direction (y), wherein M is an integer (i.e., 2) greater than 1, the second direction (y) intersects the first direction (x); and wherein along a direction (y) from a location near the signal input terminal to a location away from the signal input terminal, an area of an orthographic projection of the light emitting devices of a (j-1)th one (i.e., 1st one – RS1) of the row sets (RS1, RS2) on the plane in which the display panel (101) is located is less than an area of an orthographic projection of the light emitting devices of a jth one (i.e., 2nd one – RS2) of the row sets (RS1, RS2) on the plane in which the display panel (101) is located, wherein j (i.e., j=2) is equal to M. Note, while Lee does not explicitly disclose a specific location of the signal input terminal within the first region, Jeon does explicitly disclose a pad part (110), i.e., including the signal input terminal (CPP1), disposed in the first region (PAo) near and/or along an upper edge thereof. See, e.g., FIG. 1a and paragraphs [0110]-[0111]. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included the signal input terminal as taught by Jeon near the upper edge in the first region (151) of the display panel (101) of Lee, according to known methods to yield predictable results, for example, so that the signal input terminal does not interfere with the light emitting devices while still being included within the display area, and thus, a non-display area (or a bezel area) may not be formed. See, e.g., paragraph [0111] of Jeon. When the signal input terminal is so disposed near the upper edge in the first region (151) of Lee as taught be Jeon, the row sets (RS1, RS2) are arranged as claimed, i.e., along a direction (y) from a location near the signal input terminal (i.e., near the upper edge) to a location away (i.e., downward) from the signal input terminal. Regarding claim 12, Lee in view of Jeon as applied to claim 11 discloses the display panel according to claim 11. Lee in view of Jeon further discloses wherein each of the row sets (RS1, RS2 – see, e.g., annotated FIG. 5 of Lee herein) is at least connected to one of the signal connection lines (CPL, SPL, LCP – see, e.g., FIG. 6 of Jeon), and currents of a plurality of the signal connection lines (CPL, SPL, LCP – see, e.g., FIG. 6 of Jeon) are equal. Claims 5-6, 10, 13-14 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jeon as applied respectively to claims 1 and 11 above, and further in view of Forrest (US 5703436 A). Regarding claim 5, Lee in view of Jeon and Forrest as applied to claim 1 discloses the display panel according to claim 1. Lee does not explicitly disclose wherein: the light emitting device comprises a first light emitting chip, a second light emitting chip, and a third light emitting chip, the first light emitting chip is a red light emitting chip, the second light emitting chip is a green light emitting chip, and the third light emitting chip is a blue light emitting chip; and an effective light emitting area of the first light emitting chip is greater than an effective light emitting area of the second light emitting chip, and the effective light emitting area of the second light emitting chip is greater than an effective light emitting area of the third light emitting chip. However, in analogous art, Forrest discloses (see, e.g., FIG. 2C): wherein the light emitting device (29) comprises a first light emitting chip (22), a second light emitting chip (21), and a third light emitting chip (20), the first light emitting chip (22) is a red light emitting chip (see arrow R), the second light emitting chip (21) is a green light emitting chip (see arrow G), and the third light emitting chip (20) is a blue light emitting chip (see arrow B); and wherein an effective light emitting area of the first light emitting chip (22) is greater than an effective light emitting area of the second light emitting chip (21), and the effective light emitting area of the second light emitting chip (21) is greater than an effective light emitting area of the third light emitting chip (20). See also generally column 6, lines 59-67. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the light emitting device (29) as taught by Forrest for the light emitting devices in the display panel (101) of Lee, according to known methods to yield predictable results, for example, so that each light emitting device may be a multicolor light emitting device allowing each pixel to output a spectrum of colors and/or hues. See, e.g., column 6, lines 59-67 of Forrest. Regarding claim 6, Lee in view of Jeon and Forrest as applied to claim 5 discloses the display panel according to claim 5. Lee further discloses wherein the display panel (101) further comprises a driver substrate (see paragraph [0024] – note, the “wiring layer” including “electronic circuits” required for the display device reads on the claimed driver substrate and is hereinafter referenced by “DS”). When Lee is modified to use the light emitting device (29) of Forrest as discussed above with respect to claim 5, Lee in view of Forrest further discloses the first light emitting chip (22 – Forrest) is disposed on the driver substrate (DS – Lee), the second light emitting chip (21 – Forrest) is disposed on the first light emitting chip (22 – Forrest), the third light emitting chip (20 – Forrest) is disposed on the second light emitting chip (21 – Forrest), and an orthographic projection of the first light emitting chip (22 – Forrest) on the driver substrate (DS – Lee), an orthographic projection of the second light emitting chip (21 – Forrest) on the driver substrate (DS – Lee), and an orthographic projection of the third light emitting chip (20 – Forrest) on the driver substrate (DS – Lee) at least overlap one another. Regarding claim 10, Lee in view of Jeon and Forrest as applied to claim 6 discloses the display panel according to claim 6. Forrest further discloses wherein in overlapping portions, light (R) emitted from the first light emitting chip (22) is emitted out through the second light emitting chip (21) and the third light emitting chip (20). Regarding claim 13, Lee in view of Jeon and Forrest as applied to claim 11 discloses the display panel according to claim 11. Lee does not explicitly disclose wherein: the light emitting device comprises a first light emitting chip, a second light emitting chip, and a third light emitting chip, the first light emitting chip is a red light emitting chip, the second light emitting chip is a green light emitting chip, and the third light emitting chip is a blue light emitting chip; and an effective light emitting area of the first light emitting chip is greater than an effective light emitting area of the second light emitting chip, and the effective light emitting area of the second light emitting chip is greater than an effective light emitting area of the third light emitting chip. However, in analogous art, Forrest discloses (see, e.g., FIG. 2C): wherein the light emitting device (29) comprises a first light emitting chip (22), a second light emitting chip (21), and a third light emitting chip (20), the first light emitting chip (22) is a red light emitting chip (see arrow R), the second light emitting chip (21) is a green light emitting chip (see arrow G), and the third light emitting chip (20) is a blue light emitting chip (see arrow B); and wherein an effective light emitting area of the first light emitting chip (22) is greater than an effective light emitting area of the second light emitting chip (21), and the effective light emitting area of the second light emitting chip (21) is greater than an effective light emitting area of the third light emitting chip (20). See also generally column 6, lines 59-67. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the light emitting device (29) as taught by Forrest for the light emitting devices in the display panel (101) of Lee, according to known methods to yield predictable results, for example, so that each light emitting device may be a multicolor light emitting device allowing each pixel to output a spectrum of colors and/or hues. See, e.g., column 6, lines 59-67 of Forrest. Regarding claim 14, Lee in view of Jeon and Forrest as applied to claim 13 discloses the display panel according to claim 13. Lee further discloses wherein the display panel (101) further comprises a driver substrate (see paragraph [0024] – note, the “wiring layer” including “electronic circuits” required for the display device reads on the claimed driver substrate and is hereinafter referenced by “DS”). When Lee is modified to use the light emitting device (29) of Forrest as discussed above with respect to claim 13, Lee in view of Forrest further discloses the first light emitting chip (22 – Forrest) is disposed on the driver substrate (DS – Lee), the second light emitting chip (21 – Forrest) is disposed on the first light emitting chip (22 – Forrest), the third light emitting chip (20 – Forrest) is disposed on the second light emitting chip (21 – Forrest), and an orthographic projection of the first light emitting chip (22 – Forrest) on the driver substrate (DS – Lee), an orthographic projection of the second light emitting chip (21 – Forrest) on the driver substrate (DS – Lee), and an orthographic projection of the third light emitting chip (20 – Forrest) on the driver substrate (DS – Lee) at least overlap one another. Regarding claim 18, Lee in view of Jeon and Forrest as applied to claim 14 discloses the display panel according to claim 14. Forrest further discloses wherein in overlapping portions, light (R) emitted from the first light emitting chip (22) is emitted out through the second light emitting chip (21) and the third light emitting chip (20). Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Jeon and Forrest. Regarding claim 19, Lee discloses (see generally, e.g., FIG. 1A and annotated FIG. 5 herein): A display panel (101), comprising a pixel region (151, 152) defined in the display panel (101), wherein the pixel region (151, 152) comprises a first region (151) and a second region (152), and the display panel (101) further comprises: a plurality of light emitting devices (107, 109, 111) disposed in the first region (151) and the second region (152) (note, in FIG. 5 the light emitting devices are illustrated but are not labeled with the corresponding reference characters, however, they are label with corresponding reference characters, e.g., in FIG. 1A); and a signal connection line (see paragraph [0024] – note, the “various wiring lines” of the “wiring layer” read on the claimed signal connection line and are hereinafter referenced by “SCL”); and an area of an orthographic projection of the light emitting devices (107, 109, 111) in the second region (152) on a plane in which the display panel (101) is located is greater than an area of an orthographic projection of the light emitting devices (107, 109, 111) in the first region (151) on the plane in which the display panel (101) is located (see FIG. 5). Lee does not explicitly disclose: a signal input terminal disposed in the first region, wherein the signal input terminal is sequentially connected to the light emitting devices (107, 109, 111) in the first region (151) and the light emitting devices (107, 109, 111) in the second region (152) through the signal connection line (SCL). However, in analogous art, Jeon discloses (see generally, e.g., FIGS. 1A and 6): a signal input terminal (CPP1) disposed in the first region (PAo), wherein the signal input terminal (CPP1) is sequentially connected to the light emitting devices (Po, Pi) in the first region (PAo) and the light emitting devices (Po, Pi) in the second region (PAi) through the signal connection line (CPL). See also, e.g., paragraphs [0205]-[0206]. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included a signal terminal as taught by Jeon in the first region (151) of the display panel (101) of Lee, wherein the signal terminal is sequentially connected to the light emitting devices (107, 109, 111) in the first region (151) of Lee and the light emitting devices (107, 109, 111) in the second region (152) of Lee through the signal connection line (SCL) of Lee according to known methods to yield predictable results, for example, to provide an input through which electrical signals can be supplied to drive and/or operate the light emitting devices. The conclusion of obviousness is further supported by an “obvious to try” rational. See, e.g., MPEP § 2143(I)(E). In particular, it is found that: (1) at the relevant time, there had been a recognized problem or need in the art, namely, a need to supply a signal to drive and/or operate the light emitting devices in first and second regions of a display panel; (2) there had been a finite number of identified, predictable potential solutions to the recognized need or problem, e.g., (i) disposing a signal input terminal in the first region so as to be sequentially connected to the light emitting devices in the first region and the light emitting devices in the second region, or (ii) disposing a signal input terminal in the second region so as to be sequentially connected to the light emitting devices in the second region and the light emitting devices in the first region; and (3) one of ordinary skill in the art could have pursued the known potential solutions with a reasonable expectation of success. Lee further discloses: wherein the first region (151) and the second region (152) are disposed along a first direction (x), the light emitting devices (107, 109, 111) in the second region (152) are arranged in a quantity N of column sets (CS1, CS2) along the first direction (x), wherein N is an integer (i.e., 2) greater than 1; wherein along a direction (x) from a location near the signal input terminal to a location away from the signal input terminal (note, as modified in accordance with the teachings of Jeon, the signal terminal is disposed in the first region (151) of Lee) , an area of an orthographic projection of the light emitting devices (107, 109, 111) of a (i-1)th one (i.e., 1st one – CS1) of the column sets (CS1, CS2) on the plane in which the display panel (101) is located is less than an area of an orthographic projection of the light emitting devices (107, 109, 111) of an ith one (i.e., 2nd one – CS2) of the column sets (CS1, CS2) on the plane in which the display panel (101) is located, wherein i (i.e., i=2) is equal to N; Lee does not explicitly disclose: wherein the light emitting device comprises a first light emitting chip, a second light emitting chip, and a third light emitting chip, the first light emitting chip is a red light emitting chip, the second light emitting chip is a green light emitting chip, and the third light emitting chip is a blue light emitting chip; and wherein an effective light emitting area of the first light emitting chip is greater than an effective light emitting area of the second light emitting chip, and the effective light emitting area of the second light emitting chip is greater than an effective light emitting area of the third light emitting chip. However, in analogous art, Forrest discloses (see, e.g., FIG. 2C): wherein the light emitting device (29) comprises a first light emitting chip (22), a second light emitting chip (21), and a third light emitting chip (20), the first light emitting chip (22) is a red light emitting chip (see arrow R), the second light emitting chip (21) is a green light emitting chip (see arrow G), and the third light emitting chip (20) is a blue light emitting chip (see arrow B); and wherein an effective light emitting area of the first light emitting chip (22) is greater than an effective light emitting area of the second light emitting chip (21), and the effective light emitting area of the second light emitting chip (21) is greater than an effective light emitting area of the third light emitting chip (20). See also generally column 6, lines 59-67. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have used the light emitting device (29) as taught by Forrest for the light emitting devices in the display panel (101) of Lee, according to known methods to yield predictable results, for example, so that each light emitting device may be a multicolor light emitting device allowing each pixel to output a spectrum of colors and/or hues. See, e.g., column 6, lines 59-67 of Forrest. Regarding claim 20, Lee in view of Jeon and Forrest as applied to claim 19 discloses the display panel according to claim 19. Lee further discloses: wherein the light emitting devices (107, 109, 111) arranged in a quantity M of row sets (RS1, RS2) along a second direction (y), wherein M is an integer (i.e., 2) greater than 1, the second direction (y) intersects the first direction (x); and Lee in view of Jeon further discloses: wherein along a direction (y) from a location near the signal input terminal to a location away from the signal input terminal, an area of an orthographic projection of the light emitting devices of a (j-1)th one (i.e., 1st one – RS1) of the row sets (RS1, RS2) on the plane in which the display panel (101) is located is less than an area of an orthographic projection of the light emitting devices of a jth one (i.e., 2nd one – RS2) of the row sets (RS1, RS2) on the plane in which the display panel (101) is located, wherein j (i.e., j=2) is equal to M. See, e.g., annotated FIG. 5 of Lee herein. Note, while Lee does not explicitly disclose a specific location of the signal input terminal within the first region, Jeon does explicitly disclose a pad part (110), i.e., including the signal input terminal (CPP1), disposed in the first region (PAo) near and/or along an upper edge thereof. See, e.g., FIG. 1a and paragraphs [0110]-[0111]. It would have been obvious to and within the capabilities of one of ordinary skill in the art before the effective filing date of the claimed invention to have included the signal input terminal as taught by Jeon near the upper edge in the first region (151) of the display panel (101) of Lee, according to known methods to yield predictable results, for example, so that the signal input terminal does not interfere with the light emitting devices while still being included within the display area, and thus, a non-display area (or a bezel area) may not be formed. See, e.g., paragraph [0111] of Jeon. When the signal input terminal is so disposed near the upper edge in the first region (151) of Lee as taught be Jeon, the row sets (RS1, RS2) are arranged as claimed, i.e., along a direction (y) from a location near the signal input terminal (i.e., near the upper edge) to a location away (i.e., downward) from the signal input terminal. Allowable Subject Matter Claims 7-9 and 15-17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter. Regarding claim 7, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “a cathode layer and a cathode wiring, the cathode layer is disposed between the driver substrate and the first light emitting chip, a via hole is defined in each of the light emitting devices, the via hole penetrates the third light emitting chip, the second light emitting chip, and the first light emitting chip and exposes the cathode layer, the cathode wiring is disposed in the via hole, and the cathode wiring is connected to the cathode layer, and a cathode of the first light emitting chip, a cathode of the second light emitting chip, and a cathode of the third light emitting chip is connected to the cathode wiring,” in such a manner as to anticipate the claim or render the claim obvious. Claims 8-9 depend from claim 7, and accordingly are indicated as including allowable subject matter for at least the same reasons as claim 7. Regarding claim 15, the prior art of record, alone or in combination, fails to disclose, along with the other claimed limitations and/or features, inter alia: “a cathode layer and a cathode wiring, the cathode layer is disposed between the driver substrate and the first light emitting chip, a via hole is defined in each of the light emitting devices, the via hole penetrates the third light emitting chip, the second light emitting chip, and the first light emitting chip and exposes the cathode layer, the cathode wiring is disposed in the via hole, and the cathode wiring is connected to the cathode layer, and a cathode of the first light emitting chip, a cathode of the second light emitting chip, and a cathode of the third light emitting chip is connected to the cathode wiring,” in such a manner as to anticipate the claim or render the claim obvious. Claims 16-17 depend from claim 15, and accordingly are indicated as including allowable subject matter for at least the same reasons as claim 15. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to JOHN P CORNELY whose telephone number is (571)272-4172. The examiner can normally be reached Monday - Thursday 8:30 AM - 4:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at (571) 272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. JOHN P. CORNELY Examiner Art Unit 2812 /J.P.C./Examiner, Art Unit 2812 /DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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Prosecution Timeline

Nov 30, 2023
Application Filed
Mar 18, 2026
Non-Final Rejection — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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1-2
Expected OA Rounds
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Grant Probability
92%
With Interview (+19.0%)
3y 5m
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