DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species C, claims 1-5, 10-11, and 15-20 in the reply filed on 04/02/2026 is acknowledged.
Foreign Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed in parent Application No. CN202311246067.9, filed on 09/25/2023.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/29/2025 and 06/16/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 15-17, and 19-20 are rejected under U.S.C. 103 as being unpatentable over Li et al.; US 12,400,574 B2; 06/2022 in view of Ma et al.; US 2024/0265861 A1; 06/2022 and Liu et al.; US 2025/0089479 A1; 02/2023
Claim 1: Li discloses an organic light emitting diode (OLED) display panel ( Fig. 11 ) having a display area ( Fig. 11 display area A1 ) and a non-display area ( Fig. 11 non-display area A2 ), comprising: a substrate ( Fig. 4 substrate 11 ); a plurality of power signal lines ( Col. 7 lines 39-41 the first metal layer 20 further includes a plurality of power supply lines VDD ), a plurality of data signal lines ( Col. 3 lines 50 – 52 The first metal layer 20 includes a plurality of data lines Data disposed in the display area A1 and the extending along the first direction ), a plurality of fanout traces ( Fig. 11 fan-out lines 90 ) disposed above the substrate ( Fig. 4 #11 ), wherein the fanout traces comprises a plurality of first fanout traces ( Col. 8 lines 13-19 the data signals are transmitted from the non-display area A2 to the bottom of the display area A1 through fan-out lines 90 ) and a plurality of second fanout traces ( as discussed above ), the first fanout traces are arranged in the display area ( Fig. 11: A1 ), the second fanout traces are arranged in the non-display area ( Fig. 11: A2 ), first end of each first fanout trace is electrically connected to one data signal line of the data signal lines ( Col. 8 lines 19-21 The fan-out lines 90 are alternately arranged through the first gate layer 60 and the second gate layer 70 ), and second end of the each first fanout trace is electrically connected to one second fanout trace of the second fanout traces ( Col. 4 lines 5-8 the first transmission lines 301, data signals are transmitted from the non-display area A2 to the data line );
Li does not appear to disclose a plurality of reset signal lines disposed above the substrate and a plurality of auxiliary traces disposed as an array in the display area above the substrate, wherein the auxiliary traces comprise a plurality of vertical auxiliary lines and a plurality of horizontal auxiliary lines, the vertical auxiliary lines are disposed in a layer different from a layer where the horizontal auxiliary lines are disposed, the vertical auxiliary lines and the power signal lines extend along a first direction, the horizontal auxiliary lines and the reset signal lines extend along a second direction, and the first direction and the second direction are perpendicular to each other; wherein the horizontal auxiliary lines are disposed in a layer different from a layer where the power signal lines are disposed, the vertical auxiliary lines are disposed in a layer different from a layer where the reset signal lines are disposed, and the horizontal auxiliary lines in parallel are electrically connected with the power signal lines in parallel at intersections therebetween, and/or the vertical auxiliary lines in parallel are electrically connected to the reset signal lines in parallel at intersections therebetween to form a grid-like connection.
Ma discloses a plurality of reset signal lines ( Fig. 11 reset signal line AZ ) disposed above the substrate ( Fig. 22 substrate 100 ); a plurality of auxiliary traces ( Fig. 23 forward scan auxiliary line FS-s, reverse sweep auxiliary line BS-f, auxiliary line VDD-f , second power auxiliary line GND-f, first clock auxiliary line CK1-f, and second clock auxiliary line CK2-f ) disposed as an array in the display area ( [0130] a silicon substrate 100, wherein the silicon substrate 100 includes a display area and a peripheral area located on at least one side of the display area ) above the substrate ( Fig. 22 substrate 100 ), wherein the auxiliary traces comprise a plurality of vertical auxiliary lines ( Fig. 24 ) and a plurality of horizontal auxiliary lines ( Fig. 23 ), the vertical auxiliary lines are disposed in a layer ( Fig. 24 third conductive layer D3 ) different from a layer where the horizontal auxiliary lines are disposed ( Fig. 23 second conductive layer D2 ), the vertical auxiliary lines ( Fig. 23 FS-s, BS-f, CK1-f, and CK2-f ) and the power signal lines ( Fig. 23 VDD-f, and GND-f ) extend along a first direction, the horizontal auxiliary lines ( Fig. 24 ZSL 1, FSL1, FSL2, D3-1 through D3-9 ) and the reset signal lines ( Fig. 11A reset signal line AZ ) extend along a second direction ( [0076] a gate of the eleventh transistor is electrically connected to a reset signal line ), and the first direction and the second direction are perpendicular to each other ( signals in Fig. 23 and 24 are perpendicular ); wherein the horizontal auxiliary lines ( Fig. 23: D2 ) are disposed in a layer different from a layer where the power signal lines are disposed ( Fig. 22 first conductive layer D1 and the horizontal auxiliary lines ( Fig. 23 D2 ) in parallel are electrically connected with the power signal lines in parallel at intersections therebetween, and/or the vertical auxiliary lines in parallel are electrically connected to the reset signal lines in parallel at intersections therebetween to form a grid-like connection ( [0242] the second conductive layer D2 includes a forward scan auxiliary line FS-s, a reverse sweep auxiliary line BS-f, a first power auxiliary line VDD-f, a second power auxiliary line GND-f (take the connection of the second power auxiliary line to the ground wire as an example).
Ma does not appear to disclose the vertical auxiliary lines are disposed in a layer different from a layer where the reset signal lines are disposed.
However, Liu teaches the vertical auxiliary lines ( Fig. 7 plurality of fragments AUF ) are disposed in a layer different from a layer where the reset signal lines are disposed ( Fig. 3L first reset signal line Vint1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li and Ma to implement the vertical auxiliary lines are disposed in a layer different from a layer where the reset signal lines are disposed because this approach is used to avoid electrical shorts and interference.
Claim 2: Li, Ma, and Liu disclose the OLED display panel of claim 1 ( as discussed above ).
Li teaches a plurality of pixel units wherein each pixel unit comprises two sub-pixels ( Col. 6 lines 14-15 the display area A1 is provided with multiple sub-pixels 10 ).
Claim 15: Li, Ma, and Liu disclose the OLED display panel of claim 1 ( as discussed above ).
Li discloses a first source-drain layer ( Fig. 4 first metal layer 20 ) disposed above the substrate ( Fig. 4 #11 ) and a second source-drain layer ( Fig. 4 second metal layer 30 ) disposed on a side of the first source-drain layer away from the substrate ( Fig. 4 #11 ).
Neither Li nor Ma appear to disclose the horizontal auxiliary lines and the first source-drain layer are arranged in a same layer, and the vertical auxiliary lines and the second source-drain layer are disposed in a same layer.
However, Liu teaches the horizontal auxiliary lines ( Fig. 3E GL1) and the first source-drain layer ( Fig. 3D S1 and D1 ) are arranged in a same layer ( as shown in Fig. 3A ), and the vertical auxiliary lines ( Fig. 3P DL ) and the second source-drain layer ( Fig. 4 #30 ) are disposed in a same layer.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li and Ma to implement the horizontal auxiliary lines and the first source-drain layer are arranged in a same layer, and the vertical auxiliary lines and the second source-drain layer are disposed in a same layer because this layout approach ensures uniform brightness and optimizes OLED efficiency.
Claim 16: Li, Ma, and Liu disclose the OLED display panel of claim 15 ( as discussed above ).
Neither Li nor Ma appear to disclose the reset signal lines and the first source-drain layer are disposed in a same layer, and the power signal lines and the second source-drain layer are disposed in a same layer.
However, Liu teaches the reset signal lines ( Fig. 3E rst1 ) and the first source-drain layer ( Fig. 3D S1 and D1 ) are disposed in a same layer ( as shown in Fig. 3A ), and the power signal lines ( Fig. 1 Vdd ) and the second source-drain layer ( Fig. 3D S2 and D2 ) are disposed in a same layer ( as shown in Fig. 3A ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li and Ma to implement the reset signal lines and the first source-drain layer are disposed in a same layer, and the power signal lines and the second source-drain layer are disposed in a same layer because electrical isolation improves device performance and prevents unwanted current flow.
Claim 17: Li, Ma, and Liu disclose the OLED display panel of claim 15 ( as discussed above ).
Li does not appear to disclose a gate layer disposed above the substrate, wherein the first source-drain layer is disposed on a side of the gate layer away from the substrate, the power signal lines and the second source-drain layer are disposed in a same layer, and the reset signal lines and the gate layer are disposed in a same layer.
However, Liu teaches further comprising a gate layer ( Fig. 3E: GL1 ) disposed above the substrate ( Fig. 4A: BS ), wherein the first source-drain layer ( Fig. 3D: S1 and D1 ) is disposed on a side of the gate layer ( Fig. 3E GL1 ) away from the substrate ( Fig. 4A: BS ), the power signal lines ( Fig 1: Vdd ) and the second source-drain layer ( Fig. 3D S2 and D2 ) are disposed in a same layer ( as shown in Fig. 3A ), and the reset signal lines ( Fig. 3E: rst1 ) and the gate layer ( Fig. 3E: GL1 ) are disposed in a same layer ( as shown in Fig. 3E ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li and Ma to implement a gate layer disposed above the substrate, wherein the first source-drain layer is disposed on a side of the gate layer away from the substrate, the power signal lines and the second source-drain layer are disposed in a same layer, and the reset signal lines and the gate layer are disposed in a same layer because this approach provides for efficient current injection into the OLED pixel electrode.
Claim 19: Li, Ma, and Liu disclose the OLED display panel of claim 1 ( as discussed above ).
Neither Li nor Liu appear to disclose spacings between any two adjacent said horizontal auxiliary lines are same, and/or spacings between any two adjacent said vertical auxiliary lines are same.
However, Ma teaches spacings between any two adjacent said horizontal auxiliary lines are same ( Fig. 23 first conductive line D1 and second conductive line D2 ), and/or spacings between any two adjacent said vertical auxiliary lines are same ( Fig. 24 forward scan auxiliary line FS-f and reverse sweep signal input line FS1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li and Ma to implement spacings between any two adjacent said horizontal auxiliary lines are same, and/or spacings between any two adjacent said vertical auxiliary lines are same because this approach enhances electrical, optical, and manufacturability precision.
Claim 20: Li discloses a terminal device ( Col. 8 lines 26 – 28 The present application further provides a display terminal, including a terminal body and the above-mentioned display panel ), comprising an organic light emitting diode (OLED) display panel ( Fig. 11), wherein the OLED display panel comprises: a substrate ( Fig. 4 substrate 11 ); a plurality of power signal lines ( Col. 7 lines 39-41 the first metal layer 20 further includes a plurality of power supply lines VDD ), a plurality of data signal lines ( Col. 3 lines 50 – 52 The first metal layer 20 includes a plurality of data lines Data disposed in the display area A1 and the extending along the first direction ), a plurality of fanout traces ( Fig. 11 fan-out lines 90 ) disposed above the substrate ( Fig. 4 #11 ), wherein the fanout traces comprises a plurality of first fanout traces ( Col. 8 lines 13-19 the data signals are transmitted from the non-display area A2 to the bottom of the display area A1 through fan-out lines 90 ) and a plurality of second fanout traces ( as discussed above ), the first fanout traces are arranged in the display area ( Fig. 11: A1 ), the second fanout traces are arranged in the non-display area ( Fig. 11: A2 ), first end of each first fanout trace is electrically connected to one data signal line of the data signal lines ( Col. 8 lines 19-21 The fan-out lines 90 are alternately arranged through the first gate layer 60 and the second gate layer 70 ), and second end of the each first fanout trace is electrically connected to one second fanout trace of the second fanout traces ( Col. 4 lines 5-8 the first transmission lines 301, data signals are transmitted from the non-display area A2 to the data line ).
Li does not appear to disclose a plurality of reset signal lines disposed above the substrate and a plurality of auxiliary traces disposed as an array in the display area above the substrate, wherein the auxiliary traces comprise a plurality of vertical auxiliary lines and a plurality of horizontal auxiliary lines, the vertical auxiliary lines are disposed in a layer different from a layer where the horizontal auxiliary lines are disposed, the vertical auxiliary lines and the power signal lines extend along a first direction, the horizontal auxiliary lines and the reset signal lines extend along a second direction, and the first direction and the second direction are perpendicular to each other; wherein the horizontal auxiliary lines are disposed in a layer different from a layer where the power signal lines are disposed, the vertical auxiliary lines are disposed in a layer different from a layer where the reset signal lines are disposed, and the horizontal auxiliary lines in parallel are electrically connected with the power signal lines in parallel at intersections therebetween, and/or the vertical auxiliary lines in parallel are electrically connected to the reset signal lines in parallel at intersections therebetween to form a grid-like connection.
Ma discloses a plurality of reset signal lines ( Fig. 11 reset signal line AZ ) disposed above the substrate ( Fig. 22 substrate 100 ); a plurality of auxiliary traces ( Fig. 23 forward scan auxiliary line FS-s, reverse sweep auxiliary line BS-f, auxiliary line VDD-f , second power auxiliary line GND-f, first clock auxiliary line CK1-f, and second clock auxiliary line CK2-f ) disposed as an array in the display area ( [0130] a silicon substrate 100, wherein the silicon substrate 100 includes a display area and a peripheral area located on at least one side of the display area ) above the substrate ( Fig. 22 substrate 100 ), wherein the auxiliary traces comprise a plurality of vertical auxiliary lines ( Fig. 24 ) and a plurality of horizontal auxiliary lines ( Fig. 23 ), the vertical auxiliary lines are disposed in a layer ( Fig. 24 third conductive layer D3 ) different from a layer where the horizontal auxiliary lines are disposed ( Fig. 23 second conductive layer D2 ), the vertical auxiliary lines ( Fig. 23 FS-s, BS-f, CK1-f, and CK2-f ) and the power signal lines ( Fig. 23 VDD-f, and GND-f ) extend along a first direction, the horizontal auxiliary lines ( Fig. 24 ZSL 1, FSL1, FSL2, D3-1 through D3-9 ) and the reset signal lines ( Fig. 11A reset signal line AZ ) extend along a second direction ( [0076] a gate of the eleventh transistor is electrically connected to a reset signal line ), and the first direction and the second direction are perpendicular to each other ( signals in Fig. 23 and 24 are perpendicular ); wherein the horizontal auxiliary lines ( Fig. 23: D2 ) are disposed in a layer different from a layer where the power signal lines are disposed ( Fig. 22 first conductive layer D1 and the horizontal auxiliary lines ( Fig. 23 D2 ) in parallel are electrically connected with the power signal lines in parallel at intersections therebetween, and/or the vertical auxiliary lines in parallel are electrically connected to the reset signal lines in parallel at intersections therebetween to form a grid-like connection ( [0242] the second conductive layer D2 includes a forward scan auxiliary line FS-s, a reverse sweep auxiliary line BS-f, a first power auxiliary line VDD-f, a second power auxiliary line GND-f (take the connection of the second power auxiliary line to the ground wire as an example).
Ma does not appear to disclose the vertical auxiliary lines are disposed in a layer different from a layer where the reset signal lines are disposed.
However, Liu teaches the vertical auxiliary lines ( Fig. 7 plurality of fragments AUF ) are disposed in a layer different from a layer where the reset signal lines are disposed ( Fig. 3L first reset signal line Vint1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li and Ma to implement the vertical auxiliary lines are disposed in a layer different from a layer where the reset signal lines are disposed because this approach is used to avoid electrical shorts between orthogonal lines.
Claims 3-5, and 10 are rejected under U.S.C. 103 as being unpatentable over Li et al.; US 12,400,574 B2; 06/2022 in view of Ma et al.; US 2024/0265861 A1; 06/2022 and Liu et al.; US 2025/0089479 A1; 02/2023 as it relates to claim 2 above and further in view of Won; US 2024/0029633 A1; 07/2023
Claim 3: Li, Ma, and Liu disclose the OLED display panel of claim 2 ( as discussed above).
Li discloses the first fanout traces ( Fig. 11 fan-out lines 90 ) comprise the first traces extending along the first direction ( Fig. 11 fan-out lines in left side ) and the second traces extending along the second direction ( Fig. 11 fan-out lines in right side ), and remaining metal traces ( first metal layer 20 and second metal layer 30 ) of the plurality of metal traces that are not used as the first fanout traces ( Fig. 11 #90 ) are used as the auxiliary traces ( Col 3 lines 50-53 The first metal layer 20 includes a plurality of data lines Data disposed in the display area A1 and the extending along the first direction ), in which remaining first metal traces that are not used as the first traces are used as the vertical auxiliary lines ( as discussed above ), and remaining second metal traces ( Fig. 4 second metal layer 30 ) that are not used as the second traces are used as the horizontal auxiliary lines ( Col. 3 lines 54-56 The second metal layer 30 includes a plurality of first transmission lines 301 in the display area A1 ).
Neither Li nor Ma nor Liu appear to disclose the display area comprises a plurality of metal traces, the metal traces comprise a plurality of first metal traces extending along the first direction and a plurality of second metal traces extending along the second direction, some of the first metal traces are used as a plurality of first traces and some of the second metal traces are used as a plurality of second traces.
However, Won teaches the display area ( Fig. 5 ) comprises a plurality of metal traces ( [0240] Each of the two or more micro-lines ML1 and ML2 may include the first metal line LL and the second metal line UL. Each of a first metal line LL and a second metal line UL of the two or more micro-lines ML1 and ML2 may be formed of the same material in the same process as each of the first metal line LL and the second metal line UL of one micro-line ML, and thus, repeated descriptions thereof are omitted ), the metal traces comprise a plurality of first metal traces extending along the first direction ( as shown in Fig. 5 ) and a plurality of second metal traces extending along the second direction ( as shown in Fig. 7 ), some of the first metal traces ( Fig. 7 first metal line LL ) are used as a plurality of first traces ( as shown in Fig. 5 ) and some of the second metal traces ( Fig. 7 second metal line UL ) are used as a plurality of second traces ( as shown in Fig. 7 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Won with Li, Ma, and Liu to implement the display area comprises a plurality of metal traces, the metal traces comprise a plurality of first metal traces extending along the first direction and a plurality of second metal traces extending along the second direction, some of the first metal traces are used as a plurality of first traces and some of the second metal traces are used as a plurality of second traces because this approach minimizes signal delay, equalizes voltage, and ensures uniform current distribution for high-resolution pixel operation.
Claim 4: Li, Ma, Liu and Won disclose the OLED display panel of claim 3 ( as discussed above ).
Neither Li nor Liu nor Won appear to disclose the first traces are spaced and insulated from the vertical auxiliary lines, the second traces are spaced and insulated from the horizontal auxiliary lines, first end of each first trace is electrically connected to one said second fanout trace, and second end of the each first trace is electrically connected to one said second trace through a first via, and each second trace is electrically connected to one said data signal line through a second via.
However, Ma teaches the first traces are spaced and insulated ( [0235] Among them, an insulation layer or a dielectric layer is set between the first conductive layer D1 and the gate layer GT ) from the vertical auxiliary lines ( as shown in Fig. 23 ), the second traces are spaced and insulated ( as discussed above ) from the horizontal auxiliary lines ( as shown in Fig. 24 ), first end of each first trace is electrically connected to one said second fanout trace ( [0241] the forward scan auxiliary line FS-s is electrically connected to the gate of the forward scan transistor Z and the forward scan control signal line FS ), and second end of the each first trace is electrically connected to one said second trace through a first via ( [0230] the area marked with a black rectangle is the position of the via holes on the insulation layer/dielectric layer between the second conductive layer D2 and the first conductive layer D1 ), and each second trace is electrically connected to one said data signal line through a second via ( as shown in Fig. 24 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Ma with Li, Won, and Liu to implement the first traces are spaced and insulated from the vertical auxiliary lines, the second traces are spaced and insulated from the horizontal auxiliary lines, first end of each first trace is electrically connected to one said second fanout trace, and second end of the each first trace is electrically connected to one said second trace through a first via, and each second trace is electrically connected to one said data signal line through a second via because this approach minimizes electrical crosstalk and parasitic capacitance.
Claim 5: Li, Ma, Liu and Won disclose the OLED display panel of claim 4 ( as discussed above ).
Neither Li nor Ma nor Won appear to disclose each pixel unit comprises one said second trace and one said horizontal auxiliary line, and the second traces and the horizontal auxiliary lines are set to be a periodic arrangement in which the second traces and the horizontal auxiliary lines alternate with and are spaced apart from each other.
However, Liu teaches each pixel unit ( Fig. 1 pixel driving circuit ) comprises one said second trace ( Fig. 1 DL ) and one said horizontal auxiliary line ( Fig. 1 GL1 ), and the second traces and the horizontal auxiliary lines are set to be a periodic arrangement ( as shown in Fig. 1 ) in which the second traces and the horizontal auxiliary lines alternate with and are spaced apart from each other ( as shown in Fig. 1 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li, Won, and Ma to implement each pixel unit comprises one said second trace and one said horizontal auxiliary line, and the second traces and the horizontal auxiliary lines are set to be a periodic arrangement in which the second traces and the horizontal auxiliary lines alternate with and are spaced apart from each other because this approach compensates for electrical variations and device aging.
Claim 10: Li, Ma, Liu and Won disclose the OLED display panel of claim 5 ( as discussed above).
Neither Li nor Ma nor Won appear to disclose a dual-reset-signal pixel drive circuit, the reset signal lines comprise second reset signal lines and third reset signal lines, each pixel unit comprises one said first trace and one said vertical auxiliary line, for two adjacent pixel units, the vertical auxiliary line in one of the two adjacent pixel units is connected with the second reset signal lines in parallel at intersections between the vertical auxiliary line and the second reset signal lines, and the vertical auxiliary line in another one of the two adjacent pixel units is connected with the third reset signal lines in parallel at intersections between the vertical auxiliary line and the third reset signal lines.
However, Liu teaches a dual-reset-signal pixel drive circuit ( [0018] the array substrate further comprises: an interconnected reset signal line network; wherein the interconnected reset signal line network comprises a plurality of first reset signal lines and a plurality of fourth reset signal lines interconnected together ), the reset signal lines comprise second reset signal lines and third reset signal lines ( Fig. 3J Vint3 ), each pixel unit comprises one said first trace and one said vertical auxiliary line ( Fig. 3D D1), for two adjacent pixel units ( as shown in Fig. 3D ), the vertical auxiliary line in one of the two adjacent pixel units ( Fig. 3D D1 ) is connected with the second reset signal lines ( Fig. 3F Vint2 ) in parallel at intersections between the vertical auxiliary line ( Fig. 3D D1 ) and the second reset signal lines ( Fig. 3F Vint2), and the vertical auxiliary line ( Fig. 3D D1 ) in another one of the two adjacent pixel units is connected with the third reset signal lines ( Fig. 3J Vint3 ) in parallel at intersections between the vertical auxiliary line ( Fig. 3D D1) and the third reset signal lines ( Fig. 3J Vint3 ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li, Won, and Ma to implement a dual-reset-signal pixel drive circuit, the reset signal lines comprise second reset signal lines and third reset signal lines, each pixel unit comprises one said first trace and one said vertical auxiliary line, for two adjacent pixel units, the vertical auxiliary line in one of the two adjacent pixel units is connected with the second reset signal lines in parallel at intersections between the vertical auxiliary line and the second reset signal lines, and the vertical auxiliary line in another one of the two adjacent pixel units is connected with the third reset signal lines in parallel at intersections between the vertical auxiliary line and the third reset signal lines because this approach maintains current stability and can prevent image flicker.
Claim 11: Li, Ma, Liu and Won disclose the OLED display panel of claim 10 ( as discussed above ).
Neither Li nor Ma appear to disclose every fourth, sixth, or eighth first metal trace of the first metal traces is used as one said vertical auxiliary line, and the vertical auxiliary line is connected with the second reset signal lines in parallel at intersections between the vertical auxiliary line and the second reset signal lines, or is connected with the third reset signal lines in parallel at intersections between the one vertical auxiliary line and the third reset signal lines.
Won discloses every fourth, sixth, or eighth first metal trace of the first metal traces ( Fig. 7 UL ) is used as one said vertical auxiliary line ( [0236] the second metal line UL may be an auxiliary line ).
Won does not appear to disclose the vertical auxiliary line is connected with the second reset signal lines in parallel at intersections between the vertical auxiliary line and the second reset signal lines, or is connected with the third reset signal lines in parallel at intersections between the one vertical auxiliary line and the third reset signal lines.
However, Liu teaches the vertical auxiliary line ( Fig. 3D D1 ) is connected with the second reset signal lines ( Fig. 3F Vint2 ) in parallel at intersections between the vertical auxiliary line ( Fig. 3D D1 ) and the second reset signal lines ( Fig. 3F Vint2 ), or is connected with the third reset signal lines ( Fig. 3J Vint3 )in parallel at intersections between the one vertical auxiliary line and the third reset signal lines
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Liu with Li, Won, and Ma to implement the vertical auxiliary line is connected with the second reset signal lines in parallel at intersections between the vertical auxiliary line and the second reset signal lines, or is connected with the third reset signal lines in parallel at intersections between the one vertical auxiliary line and the third reset signal lines because this approach is used to prevent unwanted current flow through the OLED.
Claim 18 is rejected under U.S.C. 103 as being unpatentable over Li et al.; US 12,400,574 B2; 06/2022 in view of Ma et al.; US 2024/0265861 A1; 06/2022 and Liu et al.; US 2025/0089479 A1; 02/2023 as it relates to claim 15 above and further in view of Shi et al.; US 12,651,567 B2; 04/2021
Claim 18: Li, Ma, and Liu disclose the OLED display panel of claim 15 ( as discussed above ).
Neither Li nor Ma nor Liu appear to disclose at least one of the first source- drain layer and the second source-drain layer is a stacked structure of titanium/aluminum/titanium.
However, Shi teaches at least one of the first source- drain layer and the second source-drain layer is a stacked structure of titanium/aluminum/titanium ( Col 12 line 66 – Col 13 line 4 Each source-drain electrode may be made of copper (Cu), aluminum (Al), titanium (Ti), or other metal materials or alloy materials, for example, may be formed into a single-layer metal layer structure or a multi-layer metal layer structure, such as a multi-layer metal layer structure of titanium/aluminum/titanium, etc ).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, to utilize the teachings of Shi with Li, Ma, and Liu to implement at least one of the first source- drain layer and the second source-drain layer is a stacked structure of titanium/aluminum/titanium because this approach is used to optimize electrical conductivity.
Conclusion
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/K.N.F./Examiner, Art Unit 2817
/MARLON T FLETCHER/Supervisory Primary Examiner, Art Unit 2817
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