DETAILED ACTION
This correspondence is in response to the communications received 05/26/2026. Claims 17-20 and 25-31 have been canceled. Claims 1-16 and 21-24 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of claims 1-16 and 21-24 without traverse of species B in the reply filed on 05/26/2026 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 11/30/2023 has been considered by the examiner and made of record in the application file.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Objections
Claim 23 is objected to because of the following informalities: Claim 23 recites "on the internal sidewall each of the plurality of contact holes". It appears this limitation should be written as “on the internal sidewall of each of the plurality of contact holes” Appropriate correction is required.
Applicant’s Claim to Figure Comparison
It is noted that this comparison is merely for the benefit of reviewers of this office action during prosecution, to allow for an understanding of the examiner’s interpretation of the Applicant’s independent claims as compared to disclosed embodiments in Applicant’s Figures. No response or comments are necessary from Applicant.
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Regarding claim 1, a semiconductor package (100), comprising:
a redistribution substrate (140) having a first surface (140A) and a second surface (140B) opposite to each other (see Fig. 1), and including a plurality of first photosensitive insulating layers (141) and a plurality of redistribution layers (145) disposed among the plurality of first photosensitive insulating layers (see Fig. 1), the plurality of redistribution layers electrically connected to each other (see [0016]);
at least one semiconductor chip (120) disposed on the first surface of the redistribution substrate (see Fig. 1) and including a plurality of contact pads (122) electrically connected to the plurality of redistribution layers (see [0016]);
a protective insulating layer (150) including a second photosensitive insulating layer (151) disposed on the second surface of the redistribution substrate (see Fig. 1) and having a plurality of contact holes (CH), the second photosensitive insulating layer including a first surface facing and adjacent to the redistribution substrate and a second surface opposite the first surface (see Fig. 1);
a non-photosensitive insulating layer (155) buried in the second photosensitive insulating layer (see Fig. 3), wherein the non-photosensitive insulating layer is provided as an outer surface of the protective insulating layer (see Fig. 3) and is adjacent to the second surface of the second photosensitive insulating layer (see Fig. 3); and
a plurality of under bump metallurgy (UBM) connectors disposed on the protective insulating layer and connected to the plurality of redistribution layers through the plurality of contact holes, respectively (see Fig. 3),
wherein a side surface of the non-photosensitive insulating layer surrounds each of the plurality of contact holes from a plan view (see Fig. 3) and has a first inclined surface inclined with respect to a surface of the plurality of redistribution layers in a first direction, and an internal sidewall of each of the plurality of contact holes of the second photosensitive insulating layer has a second inclined surface inclined with respect to the surface of the plurality of redistribution layers in a second direction opposite to the first direction (see Fig. 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 21 and 22 are rejected under 35 U.S.C. 103 as being unpatentable over Kim et al. (US 20230025903 A1, filed 04/06/2022, hereinafter ‘903) in view of Kim et al. (US 11,094,660 B2, published 08/17/2021, hereinafter ‘660).
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Regarding claim 1, Figs. 1A-2I of ‘903 disclose a semiconductor package (see title), comprising:
a redistribution substrate (together “a second insulting layer IL2, a third insulating layer IL3, and/or redistribution patterns RP”, [0018], form a redistribution substrate) having a first surface (as seen in Fig. 1A, the top surface of IL3 is a first surface) and a second surface (as seen in Fig. 1A, the bottom surface of IL2 is a second surface) opposite to each other (as seen in Fig. 1A, the top surface of IL3 is opposite the bottom surface of IL2), and including a plurality of first photosensitive insulating layers (“IL2 and IL3 may include a photoimageable dielectric (PID)”, [0019]) and a plurality of redistribution layers (RP) disposed among the plurality of first photosensitive insulating layers (as seen in Fig. 1A, RP is disposed among IL2 and IL3);
at least one semiconductor chip (“semiconductor chip 100”, [0017]) disposed on the first surface of the redistribution substrate (as seen in Fig. 1A, 100 is disposed on the upper surface of IL3) and including a plurality of contact pads (“pads 140”, [0029]) electrically connected to the plurality of redistribution layers (as seen in Fig. 1A, 140 are electrically connect to RP via “bumps BP”, [0017]);
a protective insulating layer (together “protection layer PL”, [0018] and “first insulating layer IL1”, [0018], form a protective insulating layer where IL1 covers and therefore protects the bottommost layer of RP) having a first surface facing the second surface of the redistribution substrate (as seen in Fig. 1A, the upper surface of IL1 is facing the lower surface of IL2) and a second surface opposite the first surface (as seen in Fig. 1A, the bottom surface of PL is opposite the top surface of IL1), and including a second photosensitive insulating layer (“IL1… may include a photoimageable dielectric (PID)”, [0019]) disposed on the second surface of the redistribution substrate (as seen in Fig. 1A, IL1 is disposed on the bottom surface of IL2) and having a plurality of contact holes (as seen in Fig. 1A, IL1 has a plurality of holes where RP and “conductive patterns CP”, [0018], are located), and a non-photosensitive insulating layer (PL, where “PL may include a non-photoimageable dielectric such as silicon oxide or silicon nitride”, [0012]) disposed at an outer surface of the second photosensitive insulating layer to form the second surface of the protective insulating layer (as seen in Fig. 1A, PL is formed at an outer surface of IL1); and
Figs. 1A-2I of ‘903 fail to disclose “a plurality of under bump metallurgy (UBM) connectors each having a UBM pad disposed on the protective insulating layer and a UBM via disposed in a respective contact hole of the plurality of contact holes and electrically connected to a redistribution signal line of the plurality of redistribution layers,
wherein the non-photosensitive insulating layer contacts each UBM pad”.
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However, in a similar field of endeavor, Figs. 14-16 of ‘660 teach a plurality of under bump metallurgy (UBM) connectors (“first underbump metal layer 160A”, col. 19, lines 39-40, where 160A of ‘660 is equivalent to CP of ‘903) each having a UBM pad (“UBM pad 162a”, col. 19, lines 42-43) disposed on the protective insulating layer (as seen in Fig. 15, 162a is disposed below surface of “first passivation layer 150A”, col. 19, line 43, thus after combination with ‘903, 162a will be disposed on PL of ‘903) and a UBM via (“UBM vias 163a”, col. 19, line 41, where “In this via arrangement, even though a diameter of each of individual UBM vias 163a is reduced, a sufficient connection area may be secured, and stress may be dispersed through a plurality of UBM vias 163a to improve board level reliability of the semiconductor package 100A”, col. 19, lines 43-48) disposed in a respective contact hole of the plurality of contact holes (after combination with ‘903, 163a of ‘660 will be disposed in the respective contact holes formed by CP of ‘903) and electrically connected to a redistribution signal line of the plurality of redistribution layers (“Four UBM vias 163a connected to the redistribution layer 142 may be arranged on a UBM pad 162a”, col. 19, lines 41-43),
wherein the non-photosensitive insulating layer contacts each UBM pad (as seen in Fig. 15, 150A contacts each 162a, where the bottom portion of 150A is equivalent to PL of ‘903).
Therefore, it would have been obvious to one having ordinary skill in the art at the time the invention was effectively filed to implement “a plurality of under bump metallurgy (UBM) connectors each having a UBM pad disposed on the protective insulating layer and a UBM via disposed in a respective contact hole of the plurality of contact holes and electrically connected to a redistribution signal line of the plurality of redistribution layers,
wherein the non-photosensitive insulating layer contacts each UBM pad” as taught by ’660 in the system of ‘903 for the purpose of improving board level reliability.
Regarding claim 22, Figs. 1A-2I of ‘903 in combination with Figs. 14-16 of ‘660 disclose the semiconductor package of claim 21, Figs. 14-16 of ‘660 further disclose wherein:
the non-photosensitive insulating layer is disposed on an upper surface of each UBM pad (as seen in Fig. 15, the bottom surface of 150A equivalent to PL of ‘903, is disposed on an upper surface of 162a).
Figs. 1A-2I of ‘903 further disclose the non-photosensitive insulating layer is disposed … on an internal sidewall of each of the plurality of contact holes (as seen in Fig. 1A of ‘903, PL extends to the internal sidewall of each of the plurality of contact holes around CP).
Allowable Subject Matter
Claims 1-16 are allowed. The following is an examiner’s statement of reasons for allowance: The prior art of record does not teach or fairly suggest the semiconductor package as recited in the claims of the instant application.
Regarding claim 1, the prior art of Kim et al. (US 11,094,660 B2) in combination with Ji et al. (US 11,439,020 B2) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the structure of the protective insulating layer including the second photosensitive insulating layer and the non-photosensitive insulating layer e.g. “a non-photosensitive insulating layer buried in the second photosensitive insulating layer, wherein the non-photosensitive insulating layer is provided as an outer surface of the protective insulating layer and is adjacent to the second surface of the second photosensitive insulating layer”.
Claims 1-13 are allowable by virtue of their dependence on claim 1.
Regarding claim 14, the prior art of Kim et al. (US 11,094,660 B2) in combination with Ji et al. (US 11,439,020 B2) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the structure of the protective insulating layer including the second photosensitive insulating layer and the non-photosensitive insulating layer, and the UBM vias e.g. “a protective insulating layer including a photosensitive insulating layer disposed on the second surface of the redistribution substrate and having a plurality of contact holes, and a non-photosensitive insulating layer buried in the photosensitive insulating layer, wherein the non-photosensitive insulating layer is provided as an outer surface of the protective insulating layer; and …
wherein for each UBM via, the photosensitive insulating layer has a portion disposed between the UBM via and the non-photosensitive insulating layer in a direction parallel to the first surface of the redistribution substrate”.
Claims 15 and 16 are allowable by virtue of their dependence on claim 14.
Claims 23 and 24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not teach or fairly suggest the semiconductor package as recited in the claims of the instant application.
Regarding claim 23, the prior art of Kim et al. (US 20230025903 A1) in view of Kim et al. (US 11094660 B2) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the relative thickness of different portions of the non-photosensitive insulating layer e.g. “a portion of the non-photosensitive insulating layer on the internal sidewall each of the plurality of contact holes has a thickness less than a thickness of a portion of the non-photosensitive insulating layer on the upper surface of each UBM pad”.
Regarding claim 24, the prior art of Kim et al. (US 20230025903 A1) in view of Kim et al. (US 11094660 B2) discloses a similar semiconductor package but fails to disclose the specific claims of the instant application regarding the relative thickness of the non-photosensitive insulating layer and the protective insulating layer e.g. “the non-photosensitive insulating layer has a thickness of 10% to 40% of a total maximum thickness of the protective insulating layer”.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BENJAMIN M KUPP whose telephone number is (571)272-5608. The examiner can normally be reached Monday - Friday, 7:00 am - 4:00 pm PT.
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/BENJAMIN MICHAEL KUPP/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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