Prosecution Insights
Last updated: April 19, 2026
Application No. 18/524,036

SEMICONDUCTOR DEVICE

Non-Final OA §103
Filed
Nov 30, 2023
Examiner
MCCOY, THOMAS WILSON
Art Unit
2814
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Mirise Technologies Corporation
OA Round
1 (Non-Final)
100%
Grant Probability
Favorable
1-2
OA Rounds
3y 5m
To Grant
99%
With Interview

Examiner Intelligence

Grants 100% — above average
100%
Career Allow Rate
10 granted / 10 resolved
+32.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
3y 5m
Avg Prosecution
44 currently pending
Career history
54
Total Applications
across all art units

Statute-Specific Performance

§103
55.2%
+15.2% vs TC avg
§102
20.4%
-19.6% vs TC avg
§112
12.4%
-27.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 10 resolved cases

Office Action

§103
Attorney Docket Number: 01_4342 Filing Date: 11/30/2023 Claimed Foreign Priority Date: 01/13/2023 (JP2023-003853) Inventor: Noborio Examiner: Thomas McCoy DETAILED ACTION This Office action responds to the application filed 11/30/2023. Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as to AIA 35 U.S.C. 102 and 103 is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for a rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. Claim Interpretation Claim 1 reads “…a plurality of trench gate structures, each of which having a trench extending…” which will be interpreted as “… a plurality of trench gate structures, wherein each trench gate structure has a trench extending…”. Claim Objections Claim 1 is objected to because of the following informalities: a portion of “…an impurity layer of the first conductivity type or the second conductivity type formed opposite to the base layer through the drift layer…” is unclear and not previously shown or described. For the purposes of examination, the line will be construed to recite “…an impurity layer of the first conductivity type or the second conductivity type formed opposite to the base layer relative to the drift layer…”. Appropriate correction is required. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-3 are rejected under 35 U.S.C. 103 as being unpatentable over Naito (US 20180082996 A1) in view of Kachi (US 20180019160 A1). Regarding claim 1, Naito (see, e.g., fig.3) shows most aspects of the instant invention including a semiconductor device comprising: A drift layer (e.g., drift region 18) having a first conductivity type (see, e.g., paragraph 74 “…(N-)-type drift region 18 …”); A base layer (e.g., base region 14) having a second conductivity type (see, e.g., fig. 3 or paragraph 73 “A (P-)-type base region 14 is formed...”); An impurity layer (e.g., buffer region 20) of the first conductivity type (e.g., (N-)-type, see fig. 3) formed opposite to the base layer (e.g., base region 14) relative to the drift layer (e.g., drift region 18); A plurality of trench gate structures (e.g., plurality of trench gate portions 40 + dummy trench portions 30), wherein each trench gate structure (e.g., individual trench gate portion 40) has a trench (see, e.g., trench configuration of trench gate portion 40/30 within fig. 3) extending through the base layer (e.g., base region 14) and having a longitudinal direction (e.g., vertical direction of fig. 3) crossing a stacking direction of the drift layer (e.g., drift region 18) and the base layer (e.g., base region 14), a gate insulating film (e.g., insulating films 42 and 32) formed on a wall surface of the trench, and a gate electrode (e.g., gate conductive portions 44 and 34) formed on the gate insulating film (e.g., insulating films 42 and 32); A first impurity region (e.g., emitter 12) of the first conductivity type (see, e.g., paragraph 59 “…the emitter region 12 is of (N+)-type”) formed on a surface layer portion of the base layer (e.g., base region 14) and having an impurity concentration higher (see, e.g., paragraph 17 “The semiconductor device may further include a drift region which is provided below the base region and has a lower impurity concentration than the emitter region”) than that of the drift layer (e.g., drift region 18); A second impurity region (e.g., contact region 15 (see fig. 1, noting fig. 3 is a cross section of fig. 1)) of the second conductivity type (see, e.g., paragraph 59 “In the present example, the contact region 15 is of (P+)-type”) formed on a surface layer portion of the base layer (e.g., base region 14) and having an impurity concentration higher (see, e.g., paragraph 59 “The contact region 15, which is of the second conductivity type and has a higher impurity concentration than the base region 14, is formed in the front surface of the base region 14…”); A first electrode (e.g., emitter electrode 52) electrically connected (see, e.g., paragraph 61 “The emitter electrode 52 is connected to the emitter region 12 and the contact region 15…”) to the first impurity region (e.g., emitter 12) and the second impurity region (e.g., contact region 15); A second electrode (e.g., collector electrode 24) electrically connected to the impurity layer (e.g., buffer region 20); The first impurity region (e.g., emitter 12) and the second impurity region (e.g., contact region 15) are alternately formed along the longitudinal direction of the trench (see, e.g., figs 1 or 2, noting that fig. 3 and fig. 2 are cross sections of fig. 1); The second impurity region (e.g., contact region 15), which is viewed in the stacking direction of the drift layer (e.g., drift region 18) and the base layer (e.g., base region 14), has a first contact side (see, e.g., annotated fig. 1 or fig. 2 of Naito) in contact with a first trench (e.g., left-side trench structure 40) in a lateral direction intersecting the longitudinal direction (e.g., vertical direction), the first contact side (see, e.g., annotated fig. 1) having a predetermined length and two boundaries (e.g., left-side top and bottom contact points), and a second contact side (see, e.g., annotated fig. 1) in contact with a second trench (e.g., right-side dummy trench structure 30) adjacent to the first trench (e.g., left-side trench structure 40) in the lateral direction, the second contact side (see, e.g., annotated fig. 1) having a predetermined length and two boundaries (e.g., right-side top and bottom contact points). PNG media_image1.png 524 306 media_image1.png Greyscale Annotated Fig. 1 Naito (see, e.g., fig. 3), however, fails to show a first linear portion is defined to extend from one of the boundaries of the first contact side toward the second trench, a second linear portion is defined to extend from the other of the boundaries of the first contact side toward the second trench, a third linear portion is defined to extend from one of the boundaries of the second contact side toward the first trench, a fourth linear portion is defined to extend from the other of the boundaries of the second contact side toward the first trench, one of a first angle between the first trench and the first linear portion and a second angle between the first trench and the second linear portion is less than 90° and the other angle is less than or equal to 90°, and one of a third angle between the second trench and the third linear portion and a fourth angle between the second trench and the fourth linear portion is less than 90°, and the other angle is less than or equal to 90°. Kachi (see, e.g., fig. 37), in a similar device to Naito, teaches an impurity region (e.g., p-type region SJ2) has a first linear portion (see, e.g., annotated fig. 2) that is defined to extend from one of the boundaries of a first contact side (see, e.g., annotated fig. 2) toward a second trench (see, e.g., annotated fig. 2), a second linear portion (see, e.g., annotated fig. 2) is defined to extend from the other of the boundaries (e.g., bottom left boundary of relevant n-type source region in annotated fig. 2) of the first contact side (see, e.g., annotated fig. 2) toward the second trench (see, e.g., annotated fig. 2), a third linear portion (see, e.g., annotated fig. 2) is defined to extend from the other of the boundaries of the second contact side (see, e.g., annotated fig. 2) toward the first trench (see, e.g., annotated fig. 2), a fourth linear portion (see, e.g., annotated fig. 2) is defined to extend from the other of the boundaries of the second contact side (see, e.g., annotated fig. 2) toward the first trench (see, e.g., annotated fig. 2), one of a first angle between the first trench (see, e.g., annotated fig. 2) and the first linear portion (see, e.g., annotated fig. 2) and a second angle between the first trench (see, e.g., annotated fig. 2) and the second linear portion (see, e.g., annotated fig. 2) is less than 90° (see, e.g., annotated fig. 3 – note that the angle is substantially more acute than a right-angle) and the other angle is less than or equal to 90° (note that angle between linear portion and trench is substantially acute, thus less than 90° (and note the structure is structurally symmetrical, thus the angles on the other side are identical)), and one of a third angle between the second trench (see, e.g., annotated fig. 3) and the third linear portion (see, e.g., annotated fig. 2) and a fourth angle between the second trench (see, e.g., annotated fig. 2) and the fourth linear portion (see, e.g., annotated fig. 2) is less than 90° (see, e.g., annotated fig. 3 – note that the angle is substantially more acute than a right-angle) and the other angle is less than or equal to 90° (note that angle between linear portion and trench is substantially acute, thus less than 90° (and note the structure is structurally symmetrical, thus the angles on the other side are identical)). PNG media_image2.png 550 605 media_image2.png Greyscale Annotated Fig. 2 PNG media_image3.png 552 494 media_image3.png Greyscale Annotated Fig. 3 Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the impurity region geometry configuration of Kachi within the impurity regions of Naito, in order to optimize performance and space, and increase the total contact area of the impurity region away from the interface, expanding the amount of area available for current flow in the center of the region between trenches. Regarding claim 2, Kachi (see, e.g., fig. 37) teaches a collection of a first, second, third, and fourth angle (see, e.g., annotated fig. 3) that can be defined as θ1, θ2, θ3, and θ4 respectively, which satisfies a formula of (1/tanθ1 + 1/tanθ2) = (1/tanθ3 + 1/tanθ4) (e.g., note that all of the angles are equivalent, as the trenches are parallel and the impurity regions laid out evenly between them – and (1/x + 1/x) = (1/x + 1/x)). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the equivalent and symmetric layout of Kachi (thus providing equivalent angles between the trenches and impurity linear portions) within the layout of Naito in view of Kachi, in order to refrain from altering the current functionality into an asymmetric current configuration between the trenches. Note that Naito’s impurity regions are also laid out symmetrically between the trenches. Regarding claim 3, Kachi (see, e.g., fig. 37) teaches wherein one of the first angle (see, e.g., first angle in annotated fig. 3) and the second angle (see, e.g., second angle in annotated fig. 3) is equal to one of the third angle (see, e.g., third angle in annotated fig. 3) and the fourth angle (see, e.g., fourth angle in annotated fig. 3). Accordingly, it would have been obvious to one of ordinary skill in the art at the time of filing the invention to include the equivalent angles of Kachi within the configuration of Naito in view of Kaito for the reasons listed above, which are considered to be relevant here (see, e.g., paragraphs 6-7 regarding claim 2). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Thomas McCoy at (571) 272-0282 and between the hours of 9:30 AM to 6:30 PM (Eastern Standard Time) Monday through Friday or by e-mail via Thomas.McCoy@uspto.gov. If attempts to reach the examiner by telephone are unsuccessful, the examiner's supervisor, Wael Fahmy, can be reached on (571) 272-1705. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /THOMAS WILSON MCCOY/ Examiner, Art Unit 2814 /WAEL M FAHMY/Supervisory Patent Examiner, Art Unit 2814
Read full office action

Prosecution Timeline

Nov 30, 2023
Application Filed
Feb 27, 2026
Non-Final Rejection — §103
Apr 15, 2026
Examiner Interview Summary
Apr 15, 2026
Applicant Interview (Telephonic)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12598814
LATERAL DIODES IN STACKED TRANSISTOR TECHNOLOGIES
2y 5m to grant Granted Apr 07, 2026
Patent 12557686
SEMICONDUCTOR PACKAGE OR DEVICE WITH BARRIER LAYER
2y 5m to grant Granted Feb 17, 2026
Patent 12520559
SEMICONDUCTOR DEVICE
2y 5m to grant Granted Jan 06, 2026
Patent 12489072
SEMICONDUCTOR DEVICE WITH AIR GAP AND METHOD FOR PREPARING THE SAME
2y 5m to grant Granted Dec 02, 2025
Patent 12351451
FABRICATION OF MEMS STRUCTURES FROM FUSED SILICA FOR INERTIAL SENSORS
2y 5m to grant Granted Jul 08, 2025
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

1-2
Expected OA Rounds
100%
Grant Probability
99%
With Interview (+0.0%)
3y 5m
Median Time to Grant
Low
PTA Risk
Based on 10 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month